ctr.vhd

VHDL编写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity ctr is
	port(clk:in std_logic;
		bell_2:in std_logic;
		reset,cnt,updown,set,set_sec,set_secl:in std_logic;
		bell:out std_logic;
		led:out std_logic_vector(2 downto 0);
		sec10,sec,secl:out std_logic_vector(3 downto 0));
end ctr;
architecture behav of ctr is
	signal clk1:bit;
	signal bell_3:std_logic;
	signal num1:integer range 0 to 3;
	signal num2:integer range 0 to 3;
	signal up_down,set1,cnt1:bit;
	signal q:std_logic_vector(7 downto 0);
	signal sq1,sq2,sq3:std_logic_vector(3 downto 0);
	signal q1,q2,q3:std_logic_vector(3 downto 0);
	signal ta1,ta2,ta3:std_logic_vector(3 downto 0);
	signal tb1,tb2,tb3:std_logic_vector(3 downto 0);
	signal tc1,tc2,tc3:std_logic_vector(3 downto 0);
	begin

	dividefreq:process(clk)   
	begin
		if(clk'event and clk='1')then
			q<=q+1;
			if q="00110001"then 
				q<=(others=>'0');clk1<=not clk1;
			end if;
		end if;
	end process dividefreq;
	
	up_dwn:process(updown,reset)
	begin
		if reset='1' then
			up_down<='0';
		elsif(updown'event and updown='1')then
			up_down<=not up_down;
		end if;
	end process up_dwn;	
	
	cont0:process(cnt,reset)
	begin
		if reset='1' then
			cnt1<='0';
		elsif(cnt'event and cnt='1')then
			if(set1='0')then
				cnt1<=not cnt1;
			end if;
		end if;
	end process cont0;
	
	set_time0:process(set,reset)
	begin
		if(set'event and set='1')then
			if(cnt1<='0')then
				set1<=not set1;		
			end if;
		end if;
	end process set_time0;
	
	set_time1:process(set_secl,reset,set1,cnt1)
	begin
		if(reset='1'and set1='1')then 
			sq3<="0000";
		elsif(set1='1'and cnt1='0')then
			if(set_secl'event and set_secl='1')then
				if sq3="1001"then sq3<="0000";
				else sq3<=sq3+'1';
				end if;
			end if;		
		end if;		
	end process set_time1;	
	
	set_time2:process(set_sec,reset,set1,cnt1)
	begin
		if(reset='1'and set1='1')then 
			sq1<="0000";sq2<="0000";
		elsif (set1='1'and cnt1='0')then
			if(set_sec'event and set_sec='1')then
				if sq2="1001"then 
					sq2<="0000";
					if sq1="1001"then
						sq1<="0000";
					else sq1<=sq1+'1';
					end if;
				else sq2<=sq2+'1';
				end if;
			end if;
		end if;
	end process set_time2;
	
	save:process(set_sec,set_secl,cnt1,set1,reset)
	begin 
		if(reset='1')then
			num1<=0; num2<=0;
		elsif(cnt1='0'and set1='0')then
			if(set_secl'event and set_secl='1')then 
				if num2=3 then
					num2<=1;
				else num2<=num2+1;
				end if;
			end if;
		elsif(cnt1='1'and set1='0')then
			if(set_sec'event and set_sec='1')then
				if num1=3 then
					num1<=0;
				else num1<=num1+1;
				end if;
			end if;
		end if;
	end process save;
	
	count:process(clk1,reset,cnt1,set1)
	begin	
		if(clk1'event and clk1='1')then
		
			if(cnt1='0'and set1='0')then
				led<="000";
				if num2=1 then
					q1<=ta1;q2<=ta2;q3<=ta3;
				elsif num2=2 then
					q1<=tb1;q2<=tb2;q3<=tb3;
				elsif num2=3 then
					q1<=tc1;q2<=tc2;q3<=tc3;
				end if;
			end if;
			if(cnt1='1'and set1='0')then
				if num1=0 then 
					ta1<=q1;ta2<=q2;ta3<=q3;
				elsif num1=1 then
					tb1<=q1;tb2<=q2;tb3<=q3;
				elsif num1=2 then
					tc1<=q1;tc2<=q2;tc3<=q3;
				end if;
			end if;
			if(cnt1='1'and set1='0')then

				case up_down is
					when'0'=>
						led<="110";
						if q3="1001"then
							if q2="1001"then
								if q1="1001"then
									bell_3<='1';q1<="0000";q2<="0000";q3<="0000";
								else q1<=q1+1;q2<="0000";q3<="0000";
								end if;
							else q2<=q2+1;q3<="0000";
							end if;
						else q3<=q3+1; 
						end if;
					when'1'=>
						led<="101";
						if q3="0000"then
							if q2="0000"then 
								if q1="0000"then
									bell_3<='1';q1<="1001";q2<="1001";q3<="1001";
								else q1<=q1-1;q2<="1001";q3<="1001";
								end if;
							else q2<=q2-1;q3<="1001";
							end if;
						else q3<=q3-1;
						end if;
				end case;
			elsif reset='1'and set1='0' then 
				q1<="0000";q2<="0000";q3<="0000";
				ta1<="0000";ta2<="0000";ta3<="0000";
				tb1<="0000";tb2<="0000";tb3<="0000";
				tc1<="0000";tc2<="0000";tc3<="0000";
				bell_3<='0';
			elsif(cnt1='0' and set1='1')then
				q1<=sq1;q2<=sq2;q3<=sq3;led<="011";	
			else led<="000";
			end if;			
		end if;
	end process count;	


	sec10<=sq1 when set1='1' else q1;
	sec<=sq2 when set1='1' else q2;
	secl<=sq3 when set1='1' else q3;
	bell<=bell_3 or bell_2;
end behav;