keyboard.vhd

VHDL编写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard is 
port(clk:in std_logic;
	keyin:in std_logic_vector(3 downto 0);
	keyout:out std_logic_vector(3 downto 0);
	reset,cnt,updown,set,set_sec,set_secl:out std_logic;
	bell_1:out std_logic);
end keyboard;
architecture behav of keyboard is
	type state_type is(s0,s1);
	signal pre_state,next_state:state_type:=s0;
	signal reg:std_logic_vector(3 downto 0);
begin
	pro1:process(clk)
	begin 
		if rising_edge(clk)then
			if keyin="1111"then
				pre_state<=next_state;
			end if;
		end if;
	end process pro1; 
	
	pro2:process(pre_state,keyin)
	begin
		case pre_state is
			when s0=>
				reg<="1011";
				next_state<=s1;
			when s1=>
				reg<="0111";
				next_state<=s0;
		end case;
	end process pro2;
	
	pro3:process(clk,keyin,reg)
	begin
		if rising_edge(clk)then
			case reg&keyin is
			when "10111110"=>
				bell_1<='1';reset<='1';cnt<='0';updown<='0';
				set<='0';set_sec<='0';set_secl<='0';
			when "10111101"=>
				bell_1<='1';reset<='0';cnt<='1';updown<='0';
				set<='0';set_sec<='0';set_secl<='0';
			when "10111011"=>
				bell_1<='1';reset<='0';cnt<='0';updown<='1';
				set<='0';set_sec<='0';set_secl<='0';
			when "10110111"=>
				bell_1<='1';reset<='0';cnt<='0';updown<='0';
				set<='1';set_sec<='0';set_secl<='0';
			when "01111101"=>
				bell_1<='1';reset<='0';cnt<='0';updown<='0';
				set<='0';set_sec<='0';set_secl<='1';
			when "01111011"=>
				bell_1<='1';reset<='0';cnt<='0';updown<='0';
				set<='0';set_sec<='1';set_secl<='0';
			when others=>
				bell_1<='0';reset<='0';cnt<='0';updown<='0';
				set<='0';set_sec<='0';set_secl<='0';
			end case;
		end if;
	end process pro3;
	keyout<=reg;
end behav;