2.txt

VHDL编写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity ctr is
	port(clk:in std_logic;
		reset,cnt,updown,set,set_sec,set_secl:in std_logic;
		bell_2,led1,led2,led3:out std_logic;
		sec10,sec,secl:out std_logic_vector(3 downto 0));
end ctr;
architecture behav of ctr is
	signal clk1:bit;
	signal stop:std_logic;
	signal up_down,set1,cnt1:bit;
	signal q:std_logic_vector(7 downto 0);
	signal sq1,sq2,sq3:std_logic_vector(3 downto 0);
	signal q1,q2,q3:std_logic_vector(3 downto 0);
	type state1 is (s0,s1);
	begin

	dividefreq:process(clk)   
	begin
		if(clk'event and clk='1')then
			q<=q+1;
			if q="00110010"then 
				q<=(others=>'0');clk1<=not clk1;
			end if;
		end if;
	end process dividefreq;
	
	up_dwn:process(updown)
	begin
		if(updown'event and updown='1')then
			up_down<=not up_down;

		end if;
	end process up_dwn;
	

					
	count:process(clk1,reset,cnt1)
	begin
		if reset='1' then 

			q1<="0000";q2<="0000";q3<="0000";
			bell_2<='0';stop<='0';
		elsif (cnt='1' and stop='0') then 
			if( clk1'event and clk1='1')then
				case up_down is
					when'0'=>
						led1<='0';led2<='1';
						if q3="1001"then
							if q2="1001"then
								if q1="1001"then
									q1<="0000";q2<="0000";q3<="0000";bell_2<='1';stop<='1'; 
								else q1<=q1+1;q2<="0000";q3<="0000";
								end if;
							else q2<=q2+1;q3<="0000";
							end if;
						else q3<=q3+1; 
						end if;
					when'1'=>
						led1<='1';led2<='0';
						if q3="0000"then
							if q2="0000"then 
								if q1="0000"then
									q1<="1001";q2<="1001";q3<="1001";bell_2<='1';stop<='1';
								else q1<=q1-1;q2<="1001";q3<="1001";
								end if;
							else q2<=q2-1;q3<="1001";
							end if;
						else q3<=q3-1;
						end if;
				end case;
			end if;
		else q1<=sq1;q2<=sq2;q3<=sq3;
		end if;
	end process count;
	
	with set1 select
		sec10<=q1 when '0',
			   sq1 when '1',
			   unaffected when others;
	with set1 select
		sec<=q1 when '0',
			   sq1 when '1',
			   unaffected when others;
	with set1 select
		secl<=q1 when '0',
			   sq1 when '1',
			   unaffected when others;
end behav;