watch.tan.summary

VHDL编写的

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.000 ns
From           : keyin[1]
To             : keyboard:inst|bell_1
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 26.000 ns
From           : ctr:inst2|bell_3
To             : bell
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.000 ns
From           : keyin[1]
To             : keyboard:inst|bell_1
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 33.33 MHz ( period = 30.000 ns )
From           : ctr:inst2|q1[0]
To             : display:inst1|bcd[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : keyboard:inst|reset
To             : ctr:inst2|q3[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

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