sdramtest.tcf

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load(utils.findFile('assert.tci'));	 // load assert support

// seed file for F:\program\school_lab\SdramTest\sdramtest.cdb.a02056: c:\ti\c6000\bios\include\4.02.83\c6211.cdb
prog.load("c:/ti/c6000/bios/include/c6211.cdb");

// value changed:
//    old  SDRAM.enter a user defined heap identifier label = 0
//    new  SDRAM.enter a user defined heap identifier label = 1
prog.module("MEM").instance("SDRAM").enableHeapLabel = 1

// value changed:
//    old  SDRAM.len = 4194304
//    new  SDRAM.len = 16777216
prog.module("MEM").instance("SDRAM").len = 16777216

// add instance TSK.initTsk
initTsk = prog.module("TSK").create("initTsk");

// add instance LOG.trace
trace = prog.module("LOG").create("trace");

// value changed:
//    old  SDRAM.heap identifier label = prog.decl("segment_name", "asm")
//    new  SDRAM.heap identifier label = prog.decl("SEG0")
prog.module("MEM").instance("SDRAM").heapLabel = prog.decl("SEG0")

// value changed:
//    old  GBL.L2 Mode - CCFG(L2MODE) = "SRAM"
//    new  GBL.L2 Mode - CCFG(L2MODE) = "4-way cache"
prog.module("GBL").C621XCCFGL2MODE = "4-way cache"

// value changed:
//    old  GBL.Chip Support Library (CSL) = "6211"
//    new  GBL.Chip Support Library (CSL) = "6711"
prog.module("GBL").CHIPTYPE = "6711"

// Warning GBL.MIPS tags do not match 
// value changed:
//    old  GBL.DSP Speed In MHz (CLKOUT) = 150.0000
//    new  GBL.DSP Speed In MHz (CLKOUT) = 150
prog.module("GBL").CLKOUT = 150

// value changed:
//    old  initTsk.Priority = 1
//    new  initTsk.Priority = 15
prog.module("TSK").instance("initTsk").priority = 15

// value changed:
//    old  initTsk.Task function = prog.decl("FXN_F_nop")
//    new  initTsk.Task function = prog.decl("initTask")
prog.module("TSK").instance("initTsk").fxn = prog.decl("initTask")

// value changed:
//    old  LOG_system.buflen (words) = 64
//    new  LOG_system.buflen (words) = 512
prog.module("LOG").instance("LOG_system").bufLen = 512

// value changed:
//    old  trace.buflen (words) = 64
//    new  trace.buflen (words) = 1024
prog.module("LOG").instance("trace").bufLen = 1024

assert.add('prog.module("HWI").instance("HWI_INT14").interruptSource == prog.get("Timer_0")')

// check any and all asserts added in the script above
assert.check();

prog.gen("sdramtest");