encode_finish.v

Turbo码编码器的encode最上层模块

module encode_finish(CLK, RESET,DATA_IN, RATE_SELECT,DATA1_OUT,DATA2_OUT);//编码模块
input CLK;//时钟信号
input DATA_IN;//输入数据端口
input RATE_SELECT;//码率选择
input RESET;//复位信号
output DATA1_OUT,DATA2_OUT;//1/2和1/3码率输出端口
wire DATA1_OUT,DATA2_OUT;


wire[10:0] RAM0_ADDRESS;//Ram0地址线
wire[10:0] RAM1_ADDRESS;//Ram1地址线
wire[10:0] RAM2_ADDRESS;//Ram2地址线
wire[10:0] RAM3_ADDRESS;//Ram3地址线
wire[10:0] RAM4_ADDRESS;//Ram4地址线
wire[10:0] ROM_ADDRESS;
wire RAM0_WRITE, RAM0_READ;//Ram0读写控制线
wire RAM1_WRITE, RAM1_READ;//Ram1读写控制线
wire RAM2_WRITE, RAM2_READ;//Ram2读写控制线
wire RAM3_WRITE, RAM3_READ;//Ram3读写控制线
wire RAM4_WRITE, RAM4_READ;//Ram4读写控制线
wire RSC1_CLR;//编码器1清零控制线
wire RSC1_EN;//编码器1使能控制线
wire RSC2_CLR;//编码器2清零控制线
wire RSC2_EN;//编码器2使能控制线
wire DELETE_ENA;//删除模块1使能控制线
wire DELETE_ENB;//删除模块2使能控制线
wire DATA_OUT_RAM0;//Ram0输出
wire DATA_OUT_RAM1;//Ram1输出
wire DATA_OUT_RAM2;//Ram2输出
wire DATA_OUT_RAM3;//Ram3输出
wire DATA_OUT_RAM4;//Ram4输出
wire OUT_RSC1;//编码器1输出
wire OUT_RSC2;//编码器2输出
wire[10:0] Rom_RAM2_ADDRESS;//Rom输出作为Ram2地址线
wire[11:0] DELETE_A_ADDRESS;//删除模块1输出地制线
wire[12:0] DELETE_B_ADDRESS;//删除模块2输出地址线

/*调用个模块*/
control con_a(.clk(CLK),.rate_select(RATE_SELECT), .reset(RESET),.Ram0_write(RAM0_WRITE), .Ram0_read(RAM0_READ), .Ram1_write(RAM1_WRITE), .Ram1_read(RAM1_READ), .Ram2_write(RAM2_WRITE), .Ram2_read(RAM2_READ), .Ram3_write(RAM3_WRITE), .Ram3_read(RAM3_READ), .Ram4_write(RAM4_WRITE), .Ram4_read(RAM4_READ),.Rom_address(ROM_ADDRESS), .Ram0_address(RAM0_ADDRESS), .Ram1_address(RAM1_ADDRESS), .Ram2_address(RAM2_ADDRESS), .Ram3_address(RAM3_ADDRESS), .Ram4_address(RAM4_ADDRESS), .RSC1_en(RSC1_EN), .RSC1_clr(RSC1_CLR),.RSC2_en(RSC2_EN), .RSC2_clr(RSC2_CLR), .Delete_ena(DELETE_ENA), .Delete_enb(DELETE_ENB));//控制模块

RAM ram0(.clk(CLK),.ram_write(RAM0_WRITE),.ram_read(RAM0_READ),.address(RAM0_ADDRESS),.data_in(DATA_IN),.data_out(DATA_OUT_RAM0));//Ram0

RAM ram1(.clk(CLK),.ram_write(RAM1_WRITE),.ram_read(RAM1_READ),.address(RAM1_ADDRESS),.data_in(DATA_IN),.data_out(DATA_OUT_RAM1));//Ram1

RAM2 ram2(.clk(CLK),.ram_write(RAM2_WRITE),.ram_read(RAM2_READ),.data_in_address(RAM2_ADDRESS),.data_out_address(Rom_RAM2_ADDRESS),.data_in(DATA_IN),.data_out(DATA_OUT_RAM2));//Ram2

RSC_a rsc1(.clk(CLK),.data_in(DATA_OUT_RAM1), .RSC_clr(RSC1_CLR), .RSC_en(RSC1_EN),.out_1a(OUT_RSC1));//分量编码器1

RSC_b rsc2(.clk(CLK),.data_in(DATA_OUT_RAM2), .RSC_clr(RSC2_CLR), .RSC_en(RSC2_EN),.out_1a(OUT_RSC2));//分量编码器2

RAM ram3(.clk(CLK),.ram_write(RAM3_WRITE),.ram_read(RAM3_READ),.address(RAM3_ADDRESS),.data_in(OUT_RSC1),.data_out(DATA_OUT_RAM3));//Ram3


RAM ram4(.clk(CLK),.ram_write(RAM4_WRITE),.ram_read(RAM4_READ),.address(RAM4_ADDRESS),.data_in(OUT_RSC2),.data_out(DATA_OUT_RAM4));//Ram4

ROM rom1(.address(ROM_ADDRESS),.clock(CLK),.q(Rom_RAM2_ADDRESS));//Rom


delete_a del_a(.clk(CLK),.data_in_a(DATA_OUT_RAM0), .data_in_b(DATA_OUT_RAM3),.data_in_c(DATA_OUT_RAM4), .delete_en_a(DELETE_ENA),.del_address(DELETE_A_ADDRESS),.multi_out(DATA1_OUT));//删除模块1

delete_b del_b(.clk(CLK),.data_in_a(DATA_OUT_RAM0), .data_in_b(DATA_OUT_RAM3),.data_in_c(DATA_OUT_RAM4), .delete_en_b(DELETE_ENB),.del_address(DELETE_B_ADDRESS),.multi_out(DATA2_OUT));//删除模块2
endmodule