delete_b.v

来自「Turbo码编码器的删除模块」· Verilog 代码 · 共 51 行

module delete_b(clk,data_in_a,data_in_b,data_in_c,delete_en_b,del_address,multi_out);//1/3码率

input clk;//时钟信号
input data_in_a;//与Ram0输出相连
input data_in_b;//与Ram3输出相连
input data_in_c;//与Ram4输出相连
input delete_en_b;//删除模块使能
output[12:0] del_address;//输出地址线
output multi_out;//输出
integer i=0;
reg multi_out;
reg [12:0] del_address;
reg[1:0] count=0;

always@(posedge clk)

begin
i=i+1;
if((i<5353)&&(delete_en_b))

begin
case (count)

2'b00: multi_out=data_in_a;
2'b01: multi_out=data_in_b;
2'b10: multi_out=data_in_c;


endcase
if(count<2)
begin
count=count+2'b01;
end
else 
begin
count=2'b00;
end
del_address=del_address+1'b1;
end

else if(i>5352)
begin
i=0;
multi_out=0;
del_address=0;
end

end

       
 endmodule