fet440_adc12_10.s43

msp430f440的头程序

#include          "msp430x44x.h" // Standard Equations
;******************************************************************************
;   MSP-FET430P440 Demo - ADC12, Trigger Conversion With Timer_A
;
;   Description: Trigger an A/D conversion with Timer_A
;
;   This example shows how to trigger an A/D conversion with Timer_A.  A single 
;   ADC12 conversion on channel A0 is triggered from Timer_A.  The ADC12 
;   internal oscillator is used for sample and conversion timing.  Timer_A is 
;   configured to run continuously. AVcc is used for the reference. The 
;   conversion results are stored in ADC12MEM0 and are moved to R5 after the 
;   convserion is complete. Test by applying a voltage to channel A0, then 
;   setting and running to a break point at "jmp Mainloop." To view the 
;   conversion results, open a register window in C-Spy and view the contents 
;   of R5.
;
;
;                MSP430F449
;              ---------------
;             |               |
;             |      A0 (P6.0)|<---- Vin
;             |               |
;
;
;       M.Mitchell
;       Texas Instruments, Inc
;       January, 2002
;******************************************************************************
;------------------------------------------------------------------------------ 
main        ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov     #0A00h,SP               ; Initialize stackpointer
StopWDT     mov     #WDTPW+WDTHOLD,&WDTCTL  ; Stop watchdog
            bis.b   #BIT0,&P6SEL            ; Enable A/D channel A0
                                            ;
SetupTA     mov     #TASSEL_2+MC_2,&TACTL   ; SMCLK, Continuous up mode
            mov     #OUTMOD_3,&CCTL1        ; PWM set/reset mode for CCR1
            mov     #0FFFh,&CCR1            ; Value in CCR to triger TAOUT.1
                                            ;
SetupADC12  mov     #ADC12ON+SHT0_2,&ADC12CTL0   ; Turn on ADC12
            mov     #SHS_1+SHP,&ADC12CTL1   ; TAOUT.1 triggers sampling timer   
                                            ;            
Mainloop    bis     #ENC,&ADC12CTL0         ; Enable conversions
testIFG     bit     #BIT0,&ADC12IFG         ; Conversion done?
            jz      testIFG                 ; No, test again
            bic     #ENC,&ADC12CTL0         ; Must clear ENC before next conv.
            mov     &ADC12MEM0,R5           ; Move result
            jmp     Mainloop                ; SET BREAKPOINT HERE
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors         
;------------------------------------------------------------------------------
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ;
            END