fet440_clks2.s43

msp430f440的头程序

#include    "msp430x44x.h";  MSP430x44x Standard Definitions
;*******************************************************************************
;  MSP-FET430P440 Demo - FLL+ Output 32k xtal + HF xtal + internal DCO
;
;  Description This program demostrates using an external 32khz crystal to 
;  supply the internal ACLK, and using a high speed crystal or resonator to 
;  supply SMCLK. The MLCK for the CPU is supplied by the DCO. The 32khz crystal 
;  connects to pins Xin and Xout. The high frequency crystal or resonator
;  connects to pins XT2in and XT2out. The DCO clock is generated internally 
;  and calibrated by the 32khz crystal. The resulting ACLK is brought
;  out on P1.5, SMCLK is brought out on P1.4, and MCLK on pin P1.1. 
;  Note: 
;  External matching capacitors must be added for the high speed crystal or
;  resonator as required.
;
;                 MSP430F44x
;             -----------------
;        /|\ |              XIN|-  
;         |  |                 | 32khz crystal
;         ---|RST          XOUT|-                               
;            |                 |
;            |            XT2IN|-  
;            |                 | high speed xtal or resonator (add capacitors 
;            |           XT2OUT|-                               as needed)
;            |                 | 
;            |             P1.5|--> ACLK = 32khz crystal out
;            |                 |
;            |             P1.4|--> SMCLK = high frequency xtal or resonator out
;            |                 |
;            |             P1.1|--> MCLK = DCO frequency 
;            |                 |
;
;   B. Merritt - meb
;   Texas Instruments Inc.
;   February 2002
;-------------------------------------------------------------------------------
            ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------- 
RESET       mov.w   #0A00h,SP               ; Initialize '449 stackpointer
SetupWDT    mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; stop WDT
SetupFLL2   bis.b   #XCAP18PF,&FLL_CTL0     ; set load capacitance for 32k xtal
SetupHF     bic.b   #XT2OFF,&FLL_CTL1       ; clear bit = high freq xtal on
ClearFlag   bic.b   #XT2OF,&FLL_CTL0        ; clear high freq fault flag
            mov     #0F000h,R15             ; move delay time to register 15 
HF_Wait     dec     R15                     ; delay for xtal to start, FLL lock
            jnz     HF_Wait		    ; loop if delay not finished         
            bit.b   #XT2OF,&FLL_CTL0        ; test high freq fault flag
            jnz     ClearFlag               ; if not loop again
SwitchHF    bis.b   #SELS,&FLL_CTL1         ; is reset so switch SMCLK = HF xtal
                                            ;
SetupPorts  bis.b   #032h,&P1DIR            ;P1.1, P1.4 & P1.5 to outputs
            bis.b   #032h,&P1SEL            ;P1.1, P1.4 & P1.5 functions to output
                                            ;MCLK, SMCLK & ACLK
Mainloop    jmp     Mainloop                ;loop with CPU running
                                            ;
;------------------------------------------------------------------------------- 
;           MSP430F43x/44x interrupt vectors used         
;------------------------------------------------------------------------------- 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            END