📄 fet440_tb05.s43
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#include "msp430x44x.h"
;******************************************************************************
; MSP-FET430P440 Demo - Timer_B Toggle P5.1, TBCCR0 upmode ISR, 32kHz ACLK
;
; Description; Toggle P5.1 using software and the TB_0 ISR. Timer_B is
; configured in an upmode, thus the timer will overflow when TBTAR counts
; to TBCCR0. In this example, TBCCR0 is loaded with 1000.
; ACLK = TBCLK = LFXT1 = 32768, MCLK = SMCLK = DCO = 32xACLK = 1.048576MHz
; //*An external watch crystal on XIN XOUT is required for ACLK*//
;
; MSP430F449
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P5.1|-->LED
;
; M.Buccini
; Texas Instruments, Inc
; January 2002
;******************************************************************************
;------------------------------------------------------------------------------
ORG 01100h ; Program Start
;------------------------------------------------------------------------------
RESET mov.w #0A00h,SP ; Initialize '449 stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupFLL bis.b #XCAP14PF,&FLL_CTL0 ; Configure load caps
SetupTB mov.w #TBSSEL0+TBCLR,&TBCTL ; ACLK, clear TAB
SetupC0 mov.w #CCIE,&TBCCTL0 ; CCR0 interrupt enabled
mov.w #1000-1,&TBCCR0 ; CCR0 counts to 1000
SetupP1 bis.b #002h,&P5DIR ; P5.1 output
bis.w #MC0,&TBCTL ; Start Timer_B in upmode
eint ; Enable interrupts
;
Mainloop bis.w #LPM3,SR ; Remain in LPM3
nop ; Required only for C-spy
;
;------------------------------------------------------------------------------
TB0_ISR; Toggle P5.1
;------------------------------------------------------------------------------
xor.b #002h,&P5OUT ; Toggle P5.1
reti ;
;
;------------------------------------------------------------------------------
; Interrupt Vectors Used MSP430x44x
;------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
ORG 0FFFAh ; Timer_B0 Vector
DW TB0_ISR ;
END
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