main.c

利用ccs3.3 开发环境

#include <stdio.h>
#include "c6713dsk.h"
#include "master.h"
#include "aic23cfg.h"
#include "dsk6713_aic23.h"
#include <std.h>
#include <swi.h>
#include <log.h>
#include <c6x.h>
#include <csl.h>
#include <csl_mcbsp.h>

/* Length of sine wave table */
#define SINE_TABLE_SIZE  48
/* Pre-generated sine wave data, 16-bit signed samples */
int sinetable[SINE_TABLE_SIZE] = {
    0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,
    0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,
    0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,
    0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,
    0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,
    0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c
};
DSK6713_AIC23_Config config = { \
    0x0017,  /* 0 DSK6713_AIC23_LEFTINVOL  Left line input channel volume */ \
    0x0017,  /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\
    0x00d8,  /* 2 DSK6713_AIC23_LEFTHPVOL  Left channel headphone volume */  \
    0x00d8,  /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \
    0x0011,  /* 4 DSK6713_AIC23_ANAPATH    Analog audio path control */      \
    0x0000,  /* 5 DSK6713_AIC23_DIGPATH    Digital audio path control */     \
    0x0000,  /* 6 DSK6713_AIC23_POWERDOWN  Power down control */             \
    0x0043,  /* 7 DSK6713_AIC23_DIGIF      Digital audio interface format */ \
    0x0081,  /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */            \
    0x0001   /* 9 DSK6713_AIC23_DIGACT     Digital interface activation */   \
};

void init_emif( void );
void init_pll ( void );
Int16 TEST_mcbsp(int devid, Int16 delayed);
Int16 TEST_codec();
main()
{ 
   LOG_printf(&trace,"board test is starting........\n");
   ISTP=0x400;
   init_pll(); 
   init_emif();
   TEST_mcbsp(MCBSP_DEV1,0);
   TEST_codec();
}

Int16 TEST_codec()
{
    DSK6713_AIC23_CodecHandle hCodec;
    Int16 i, j;

    /* Start the codec */
    hCodec = DSK6713_AIC23_openCodec(0, &config);
    
    /* Generate a 1KHz sine wave for 1 second */
    for (i = 0; i < 1000; i++)
    {
        for (j = 0; j < SINE_TABLE_SIZE; j++)
        {       
            while (!DSK6713_AIC23_write(hCodec, sinetable[j]));
            while (!DSK6713_AIC23_write(hCodec, sinetable[j]));
        }
    }
    
    /* Close codec */
  //  DSK6713_AIC23_closeCodec(hCodec);

    return 0;
}
Int16 TEST_mcbsp(int devid, Int16 delayed)
{
    Int16 i;
    Uint16 receivedata;
    MCBSP_Handle hMcbsp;
    short src[30],dst[30];
    MCBSP_Config mcbspCfg_loopback = {
        MCBSP_FMKS(SPCR, FREE, NO)              |
        MCBSP_FMKS(SPCR, SOFT, NO)              |
        MCBSP_FMKS(SPCR, FRST, YES)             |
        MCBSP_FMKS(SPCR, GRST, YES)             |
        MCBSP_FMKS(SPCR, XINTM, XRDY)           |
        MCBSP_FMKS(SPCR, XSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, XRST, YES)             |
        MCBSP_FMKS(SPCR, DLB, ON)               |
        MCBSP_FMKS(SPCR, RJUST, RZF)            |
        MCBSP_FMKS(SPCR, CLKSTP, DISABLE)       |
        MCBSP_FMKS(SPCR, DXENA, OFF)            |
        MCBSP_FMKS(SPCR, RINTM, RRDY)           |
        MCBSP_FMKS(SPCR, RSYNCERR, NO)          |
        MCBSP_FMKS(SPCR, RRST, YES),
        
        MCBSP_FMKS(RCR, RPHASE, SINGLE)         |
        MCBSP_FMKS(RCR, RFRLEN2, DEFAULT)       |
        MCBSP_FMKS(RCR, RWDLEN2, DEFAULT)       |
        MCBSP_FMKS(RCR, RCOMPAND, MSB)          |
        MCBSP_FMKS(RCR, RFIG, NO)               |
        MCBSP_FMKS(RCR, RDATDLY, 0BIT)          |
        MCBSP_FMKS(RCR, RFRLEN1, OF(0))         |
        MCBSP_FMKS(RCR, RWDLEN1, 16BIT)         |
        MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

        MCBSP_FMKS(XCR, XPHASE, SINGLE)         |
        MCBSP_FMKS(XCR, XFRLEN2, DEFAULT)       |
        MCBSP_FMKS(XCR, XWDLEN2, DEFAULT)       |
        MCBSP_FMKS(XCR, XCOMPAND, MSB)          |
        MCBSP_FMKS(XCR, XFIG, NO)               |
        MCBSP_FMKS(XCR, XDATDLY, 0BIT)          |
        MCBSP_FMKS(XCR, XFRLEN1, OF(0))         |
        MCBSP_FMKS(XCR, XWDLEN1, 16BIT)         |
        MCBSP_FMKS(XCR, XWDREVRS, DISABLE),
        
        MCBSP_SRGR_DEFAULT,
        MCBSP_MCR_DEFAULT,
        MCBSP_RCER_DEFAULT,
        MCBSP_XCER_DEFAULT,
        
        MCBSP_FMKS(PCR, XIOEN, DEFAULT)         |
        MCBSP_FMKS(PCR, RIOEN, DEFAULT)         |
        MCBSP_FMKS(PCR, FSXM, INTERNAL)         |
        MCBSP_FMKS(PCR, FSRM, DEFAULT)          |
        MCBSP_FMKS(PCR, CLKXM, OUTPUT)          |
        MCBSP_FMKS(PCR, CLKRM, INPUT)           |
        MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT)      |
        MCBSP_FMKS(PCR, DXSTAT, DEFAULT)        |
        MCBSP_FMKS(PCR, FSXP, DEFAULT)          |
        MCBSP_FMKS(PCR, FSRP, DEFAULT)          |
        MCBSP_FMKS(PCR, CLKXP, DEFAULT)         |
        MCBSP_FMKS(PCR, CLKRP, DEFAULT)           
    };
            
    /* Initialize source data, zero dest */
    for (i = 0; i < 20; i++)
     {
        src[i] = (i << 8) | i + 1;
        dst[i] = 0;
     }

    /* Open the McBSP */
    hMcbsp = MCBSP_open(devid, MCBSP_OPEN_RESET);
    
    /* Configure the McBSP for loopback mode */
    MCBSP_config(hMcbsp, &mcbspCfg_loopback);

    /* Start the McBSP */
    MCBSP_start(hMcbsp, MCBSP_RCV_START | MCBSP_XMIT_START |
        MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, MCBSP_SRGR_DEFAULT_DELAY);
        
    /* Data transfer loop */
    for (i = 0; i < (20 + delayed); i++) {
        /* Wait for XRDY signal before writing data to DXR */
        while (!MCBSP_xrdy(hMcbsp));       
                 
        /* Write 16 bit data value to DXR */
        MCBSP_write(hMcbsp,src[i]);       
 
        /* Wait for RRDY signal to read data from DRR */
        while (!MCBSP_rrdy(hMcbsp));

        /* Read 16 bit value from DRR */
        receivedata = MCBSP_read(hMcbsp);
        if (i >= delayed)
            dst[i - delayed] = receivedata;               
    }

    /* Close the McBSP */
    MCBSP_close(hMcbsp);

    /* Check data to make sure transfer was successful */
    for (i = 0; i <20; i++)
        if (dst[i] != src[i])
            return 1;
    
    /* Test passed */
    return 0;
}


void init_emif( void )
{
	*(int *)EMIF_GCTL     = 0x00000078;
	*(int *)EMIF_CE3      = 0xffffff13; 
	*(int *)EMIF_CE0      = 0xffffff23; 
	*(int *)EMIF_CE1      = 0xffffff13;  /* CE1 Flash 16-bit               */
	*(int *)EMIF_CE2      = 0xffffff93;  /* CE2 SDRAM                     */
	*(int *)EMIF_SDRAMCTL = 0x53115000;  /* SDRAM control                 */
	*(int *)EMIF_SDRAMTIM = 0x00000578;  /* SDRAM timing (refresh)        */
	*(int *)EMIF_SDRAMEXT = 0x000a8529;  /* SDRAM Extension register      */
}
setpll200M()
{

}
void  init_pll( void )
{
    *(int *)PLL_CSR  &= ~CSR_PLLEN;         // 不使能PLL
    *(int *)PLL_CSR  |= CSR_PLLRST;         // PLL-RESET
    *(int *)PLL_DIV0    = DIV_ENABLE + 0;   // 分频器0--1分频
    *(int *)PLL_MULT    = 8;                // 8倍频==400M HZ
    *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4;   // CLKOUT3--5分频===10MHZ
    *(int *)PLL_DIV3    = DIV_ENABLE + 3;   // ECLKOUT---4分频===100MHZ
    *(int *)PLL_DIV2    = DIV_ENABLE + 3;   // SYSCLK-----4分频==100MHZ
    *(int *)PLL_DIV1    = DIV_ENABLE + 1;   // DSP--CORE----2分频==200MHZ
    *(int *)PLL_CSR  &= ~CSR_PLLRST;        // PLL--RESET  END
    *(int *)PLL_CSR |= CSR_PLLEN;         // PLL--ENABLE
}