led_pili_f_s.tan.rpt

来自「16bit霹靂燈 LED左右來回跑 時快時慢 也可以設定成跑馬燈形式」· RPT 代码 · 共 400 行 · 第 1/5 页

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Wed May 20 18:29:37 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LED_PILI_F_S -c LED_PILI_F_S --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "SHIFT_DIV" as buffer
    Info: Detected ripple clock "DIVIDER[29]" as buffer
    Info: Detected ripple clock "DIVIDER[23]" as buffer
    Info: Detected ripple clock "DIVIDER[25]" as buffer
Info: Clock "CLK" has Internal fmax of 234.25 MHz between source register "DIVIDER[1]" and destination register "DIVIDER[29]" (period= 4.269 ns)
    Info: + Longest register to register delay is 3.502 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N1; Fanout = 3; REG Node = 'DIVIDER[1]'
        Info: 2: + IC(0.497 ns) + CELL(0.414 ns) = 0.911 ns; Loc. = LCCOMB_X1_Y18_N4; Fanout = 2; COMB Node = 'DIVIDER[2]~171'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.982 ns; Loc. = LCCOMB_X1_Y18_N6; Fanout = 2; COMB Node = 'DIVIDER[3]~173'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.053 ns; Loc. = LCCOMB_X1_Y18_N8; Fanout = 2; COMB Node = 'DIVIDER[4]~175'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.124 ns; Loc. = LCCOMB_X1_Y18_N10; Fanout = 2; COMB Node = 'DIVIDER[5]~177'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.195 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 2; COMB Node = 'DIVIDER[6]~179'
        Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 1.354 ns; Loc. = LCCOMB_X1_Y18_N14; Fanout = 2; COMB Node = 'DIVIDER[7]~181'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.425 ns; Loc. = LCCOMB_X1_Y18_N16; Fanout = 2; COMB Node = 'DIVIDER[8]~183'
        Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.496 ns; Loc. = LCCOMB_X1_Y18_N18; Fanout = 2; COMB Node = 'DIVIDER[9]~185'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.567 ns; Loc. = LCCOMB_X1_Y18_N20; Fanout = 2; COMB Node = 'DIVIDER[10]~187'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.638 ns; Loc. = LCCOMB_X1_Y18_N22; Fanout = 2; COMB Node = 'DIVIDER[11]~189'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.709 ns; Loc. = LCCOMB_X1_Y18_N24; Fanout = 2; COMB Node = 'DIVIDER[12]~191'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.780 ns; Loc. = LCCOMB_X1_Y18_N26; Fanout = 2; COMB Node = 'DIVIDER[13]~193'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.851 ns; Loc. = LCCOMB_X1_Y18_N28; Fanout = 2; COMB Node = 'DIVIDER[14]~195'
        Info: 15: + IC(0.000 ns) + CELL(0.146 ns) = 1.997 ns; Loc. = LCCOMB_X1_Y18_N30; Fanout = 2; COMB Node = 'DIVIDER[15]~197'
        Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 2.068 ns; Loc. = LCCOMB_X1_Y17_N0; Fanout = 2; COMB Node = 'DIVIDER[16]~199'
        Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 2.139 ns; Loc. = LCCOMB_X1_Y17_N2; Fanout = 2; COMB Node = 'DIVIDER[17]~201'
        Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.210 ns; Loc. = LCCOMB_X1_Y17_N4; Fanout = 2; COMB Node = 'DIVIDER[18]~203'
        Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.281 ns; Loc. = LCCOMB_X1_Y17_N6; Fanout = 2; COMB Node = 'DIVIDER[19]~205'
        Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.352 ns; Loc. = LCCOMB_X1_Y17_N8; Fanout = 2; COMB Node = 'DIVIDER[20]~207'
        Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.423 ns; Loc. = LCCOMB_X1_Y17_N10; Fanout = 2; COMB Node = 'DIVIDER[21]~209'
        Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.494 ns; Loc. = LCCOMB_X1_Y17_N12; Fanout = 2; COMB Node = 'DIVIDER[22]~211'
        Info: 23: + IC(0.000 ns) + CELL(0.159 ns) = 2.653 ns; Loc. = LCCOMB_X1_Y17_N14; Fanout = 2; COMB Node = 'DIVIDER[23]~213'
        Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.724 ns; Loc. = LCCOMB_X1_Y17_N16; Fanout = 2; COMB Node = 'DIVIDER[24]~215'
        Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 2.795 ns; Loc. = LCCOMB_X1_Y17_N18; Fanout = 2; COMB Node = 'DIVIDER[25]~217'
        Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 2.866 ns; Loc. = LCCOMB_X1_Y17_N20; Fanout = 2; COMB Node = 'DIVIDER[26]~219'
        Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 2.937 ns; Loc. = LCCOMB_X1_Y17_N22; Fanout = 2; COMB Node = 'DIVIDER[27]~221'
        Info: 28: + IC(0.000 ns) + CELL(0.071 ns) = 3.008 ns; Loc. = LCCOMB_X1_Y17_N24; Fanout = 1; COMB Node = 'DIVIDER[28]~223'
        Info: 29: + IC(0.000 ns) + CELL(0.410 ns) = 3.418 ns; Loc. = LCCOMB_X1_Y17_N26; Fanout = 1; COMB Node = 'DIVIDER[29]~224'
        Info: 30: + IC(0.000 ns) + CELL(0.084 ns) = 3.502 ns; Loc. = LCFF_X1_Y17_N27; Fanout = 2; REG Node = 'DIVIDER[29]'
        Info: Total cell delay = 3.005 ns ( 85.81 % )
        Info: Total interconnect delay = 0.497 ns ( 14.19 % )
    Info: - Smallest clock skew is -0.553 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.123 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.587 ns) + CELL(0.537 ns) = 2.123 ns; Loc. = LCFF_X1_Y17_N27; Fanout = 2; REG Node = 'DIVIDER[29]'
            Info: Total cell delay = 1.536 ns ( 72.35 % )
            Info: Total interconnect delay = 0.587 ns ( 27.65 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.676 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 26; COMB Node = 'CLK~clkctrl'
            Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y18_N1; Fanout = 3; REG Node = 'DIVIDER[1]'
            Info: Total cell delay = 1.536 ns ( 57.40 % )
            Info: Total interconnect delay = 1.140 ns ( 42.60 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "CLK" to destination pin "LED[5]" through register "COUNT[5]" is 9.514 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.507 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.587 ns) + CELL(0.787 ns) = 2.373 ns; Loc. = LCFF_X1_Y17_N19; Fanout = 3; REG Node = 'DIVIDER[25]'
        Info: 3: + IC(0.319 ns) + CELL(0.420 ns) = 3.112 ns; Loc. = LCCOMB_X1_Y17_N28; Fanout = 1; COMB Node = 'SHIFT_DIV'
        Info: 4: + IC(0.820 ns) + CELL(0.000 ns) = 3.932 ns; Loc. = CLKCTRL_G0; Fanout = 17; COMB Node = 'SHIFT_DIV~clkctrl'
        Info: 5: + IC(1.038 ns) + CELL(0.537 ns) = 5.507 ns; Loc. = LCFF_X61_Y35_N13; Fanout = 3; REG Node = 'COUNT[5]'
        Info: Total cell delay = 2.743 ns ( 49.81 % )
        Info: Total interconnect delay = 2.764 ns ( 50.19 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.757 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y35_N13; Fanout = 3; REG Node = 'COUNT[5]'
        Info: 2: + IC(0.978 ns) + CELL(2.779 ns) = 3.757 ns; Loc. = PIN_F20; Fanout = 0; PIN Node = 'LED[5]'
        Info: Total cell delay = 2.779 ns ( 73.97 % )
        Info: Total interconnect delay = 0