📄 led.fit.rpt
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Fitter report for LED
Wed May 20 19:35:24 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Incremental Compilation Preservation Summary
5. Incremental Compilation Partition Settings
6. Incremental Compilation Placement Preservation
7. Pin-Out File
8. Fitter Resource Usage Summary
9. Input Pins
10. Output Pins
11. I/O Bank Usage
12. All Package Pins
13. Output Pin Default Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Delay Chain Summary
16. Pad To Core Delay Chain Fanout
17. Control Signals
18. Global & Other Fast Signals
19. Non-Global High Fan-Out Signals
20. Interconnect Usage Summary
21. LAB Logic Elements
22. LAB-wide Signals
23. LAB Signals Sourced
24. LAB Signals Sourced Out
25. LAB Distinct Inputs
26. Fitter Device Options
27. Operating Settings and Conditions
28. Estimated Delay Added for Hold Timing
29. Advanced Data - General
30. Advanced Data - Placement Preparation
31. Advanced Data - Placement
32. Advanced Data - Routing
33. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-----------------------------------------+
; Fitter Status ; Successful - Wed May 20 19:35:24 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; LED ;
; Top-level Entity Name ; LED ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 57 / 33,216 ( < 1 % ) ;
; Total combinational functions ; 52 / 33,216 ( < 1 % ) ;
; Dedicated logic registers ; 46 / 33,216 ( < 1 % ) ;
; Total registers ; 46 ;
; Total pins ; 18 / 475 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C35F672C6 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
; Maximum number of global clocks allowed ; -1 ; -1 ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type ; Value ;
+-------------------------+--------------------+
; Placement ; ;
; -- Requested ; 0 / 116 ( 0.00 % ) ;
; -- Achieved ; 0 / 116 ( 0.00 % ) ;
; ; ;
; Routing (by Connection) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
; -- Achieved ; 0 / 0 ( 0.00 % ) ;
+-------------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top ; 116 ; 0 ; N/A ; Source File ;
+----------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/⌨️ 快捷键说明
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