📄 led_pili_f_s.vhd
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LED_PILI_F_S is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (15 downto 0));
end LED_PILI_F_S;
architecture Behavioral of LED_PILI_F_S is
signal DIVIDER : STD_LOGIC_VECTOR (29 downto 1);
signal SL_DIV : STD_LOGIC;
signal FL_DIV : STD_LOGIC;
signal DE_DIV : STD_LOGIC;
signal SHIFT_DIV : STD_LOGIC;
signal DIR : STD_LOGIC;
begin
process(CLK,RESET)
begin
if RESET='0' then
DIVIDER <= (others => '0');
elsif CLK'event and CLK='1' then
DIVIDER <= DIVIDER + 1;
end if;
end process;
SL_DIV <= DIVIDER(25);
FL_DIV <= DIVIDER(23);
DE_DIV <= DIVIDER(29);
SHIFT_DIV <= FL_DIV when DE_DIV = '1' else SL_DIV;
process(SHIFT_DIV,RESET)
variable COUNT : STD_LOGIC_VECTOR (15 downto 0);
begin
if RESET='0' then
COUNT := x"C000";
DIR <= '0';
elsif SHIFT_DIV'event and SHIFT_DIV='1' then
if DIR = '0' then
COUNT := COUNT(0) & COUNT(15 downto 1);
else
COUNT := COUNT(14 downto 0) & COUNT(15);
end if;
if COUNT = x"0003" then
DIR <= '1';
elsif COUNT = x"C000" then
DIR <= '0';
end if;
end if;
LED <= COUNT;
end process;
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -