cstartup_sam7.lst

针对at91sam7a3为主芯片开发板开发的spi口应用程序

   \   00000024   FCD5               BPL         ??AT91F_LowLevelInit_2
     60              // Wait until the master clock is established for the case we already turn on the PLL
     61              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_3:
   \   00000026   0821               MOV         R1,#+0x8
   \   00000028   0268               LDR         R2,[R0, #+0]
   \   0000002A   0A42               TST         R2,R1
   \   0000002C   FBD0               BEQ         ??AT91F_LowLevelInit_3
     62          
     63              /////////////////////////////////////////////////////////////////////////////////////////////////////
     64              // Init PMC Step 3.
     65              // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
     66              // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
     67              /////////////////////////////////////////////////////////////////////////////////////////////////////
     68              AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
   \   0000002E   184A               LDR         R2,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000030   0423               MOV         R3,#+0x4
   \   00000032   1360               STR         R3,[R2, #+0]
     69              // Wait until the master clock is established
     70              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_4:
   \   00000034   0368               LDR         R3,[R0, #+0]
   \   00000036   0B42               TST         R3,R1
   \   00000038   FCD0               BEQ         ??AT91F_LowLevelInit_4
     71          
     72              AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
   \   0000003A   1368               LDR         R3,[R2, #+0]
   \   0000003C   0324               MOV         R4,#+0x3
   \   0000003E   1C43               ORR         R4,R3
   \   00000040   1460               STR         R4,[R2, #+0]
     73              // Wait until the master clock is established
     74              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_5:
   \   00000042   0268               LDR         R2,[R0, #+0]
   \   00000044   0A42               TST         R2,R1
   \   00000046   FCD0               BEQ         ??AT91F_LowLevelInit_5
     75          
     76              /////////////////////////////////////////////////////////////////////////////////////////////////////
     77              //  Disable Watchdog (write once register)
     78              /////////////////////////////////////////////////////////////////////////////////////////////////////
     79              AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
   \   00000048   1248               LDR         R0,??AT91F_LowLevelInit_0+0x18  ;; 0xfffffd44
   \   0000004A   0903               LSL         R1,R1,#+0xC
   \   0000004C   0160               STR         R1,[R0, #+0]
     80          
     81              /////////////////////////////////////////////////////////////////////////////////////////////////////
     82              //  Enable User Reset: assertion of the Reset Length programmed to 1ms
     83              /////////////////////////////////////////////////////////////////////////////////////////////////////
     84              AT91C_BASE_RSTC->RSTC_RMR = AT91C_RSTC_URSTEN | (0x4<<8) | ((unsigned int) 0xA5 <<24);
   \   0000004E   1248               LDR         R0,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffffd08
   \   00000050   1249               LDR         R1,??AT91F_LowLevelInit_0+0x20  ;; 0xa5000401
   \   00000052   0160               STR         R1,[R0, #+0]
     85          
     86              ////////////////////////////////////////////////////////////////////////////////////////////////////
     87              //  Init AIC: assign corresponding handler for each interrupt source
     88              /////////////////////////////////////////////////////////////////////////////////////////////////////
     89              AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
   \   00000054   1248               LDR         R0,??AT91F_LowLevelInit_0+0x24  ;; 0xfffff080
   \   00000056   1349               LDR         R1,??AT91F_LowLevelInit_0+0x28  ;; AT91F_Default_FIQ_handler
   \   00000058   0160               STR         R1,[R0, #+0]
     90              for (i = 1; i < 31; i++) {
   \   0000005A   0120               MOV         R0,#+0x1
   \   0000005C   104A               LDR         R2,??AT91F_LowLevelInit_0+0x24  ;; 0xfffff080
   \   0000005E   124B               LDR         R3,??AT91F_LowLevelInit_0+0x2C  ;; AT91F_Default_IRQ_handler
     91                  AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
   \                     ??AT91F_LowLevelInit_6:
   \   00000060   8100               LSL         R1,R0,#+0x2
   \   00000062   5350               STR         R3,[R2, R1]
     92              }
   \   00000064   401C               ADD         R0,R0,#+0x1
   \   00000066   0106               LSL         R1,R0,#+0x18
   \   00000068   090E               LSR         R1,R1,#+0x18
   \   0000006A   1F29               CMP         R1,#+0x1F
   \   0000006C   F8D3               BCC         ??AT91F_LowLevelInit_6
     93              AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
   \   0000006E   0F48               LDR         R0,??AT91F_LowLevelInit_0+0x30  ;; 0xfffff134
   \   00000070   0F49               LDR         R1,??AT91F_LowLevelInit_0+0x34  ;; AT91F_Spurious_handler
   \   00000072   0160               STR         R1,[R0, #+0]
     94          }
   \   00000074   10BC               POP         {R4}
   \   00000076   01BC               POP         {R0}
   \   00000078   0047               BX          R0                 ;; return
   \   0000007A   C046               NOP         
   \                     ??AT91F_LowLevelInit_0:
   \   0000007C   20FCFFFF           DC32        0xfffffc20
   \   00000080   01400000           DC32        0x4001
   \   00000084   68FCFFFF           DC32        0xfffffc68
   \   00000088   2CFCFFFF           DC32        0xfffffc2c
   \   0000008C   0E3F4810           DC32        0x10483f0e
   \   00000090   30FCFFFF           DC32        0xfffffc30
   \   00000094   44FDFFFF           DC32        0xfffffd44
   \   00000098   08FDFFFF           DC32        0xfffffd08
   \   0000009C   010400A5           DC32        0xa5000401
   \   000000A0   80F0FFFF           DC32        0xfffff080
   \   000000A4   ........           DC32        AT91F_Default_FIQ_handler
   \   000000A8   ........           DC32        AT91F_Default_IRQ_handler
   \   000000AC   34F1FFFF           DC32        0xfffff134
   \   000000B0   ........           DC32        AT91F_Spurious_handler

   Maximum stack usage in bytes:

     Function           CSTACK
     --------           ------
     AT91F_LowLevelInit     8


   Segment part sizes:

     Function/Label     Bytes
     --------------     -----
     AT91F_LowLevelInit  180
      Others               8

 
 188 bytes in segment CODE
 
 180 bytes of CODE memory (+ 8 bytes shared)

Errors: none
Warnings: none