📄 hardware.lst
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0000983C 19 D3 10 70 [P_INT_Ctrl] = r1 //
0000983E 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S480_Initial()
// or F_SACM_S480_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S480_Init_:
0000983F 40 92 r1 = 0x0000 // 24MHz Fosc
00009840 19 D3 13 70 [P_SystemClock]=r1 // Initial System Clock
00009842 70 92 r1=0x0030 // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009843 19 D3 0B 70 [P_TimerA_Ctrl]=r1 // Initial Timer A
//R1 = 0xfd00 // 16K
00009845 09 93 ED FC r1 = 0xfced // 15.625K
00009847 19 D3 0A 70 [P_TimerA_Data]=r1
00009849 09 93 A8 00 r1 = 0x00A8 //
0000984B 19 D3 2A 70 [P_DAC_Ctrl] = r1 //
0000984D 09 93 FF FF r1 = 0xffff
0000984F 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00009851 11 93 89 05 R1 = [R_InterruptStatus] //
00009853 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
//R1 |= C_IRQ4_1KHz // Enable 1KHz IRQ4 for S480 decoder
00009855 19 D3 89 05 [R_InterruptStatus] = r1 //
00009857 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009859 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_S240_Initial()
// or F_SACM_S240_Initial:
//////////////////////////////////////////////////////////////////
F_SP_SACM_S240_Init_:
0000985A 60 92 r1=0x0020;
0000985B 19 D3 13 70 [P_SystemClock]=r1
0000985D 09 93 A8 00 r1 = 0x00A8; //
0000985F 19 D3 2A 70 [P_DAC_Ctrl]= r1
00009861 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009862 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
00009864 09 93 00 FE r1 = 0xfe00; // 24K
00009866 19 D3 0A 70 [P_TimerA_Data] = r1;
00009868 09 93 FF FF r1 = 0xffff
0000986A 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
0000986C 11 93 89 05 r1 = [R_InterruptStatus] //
0000986E 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
00009870 19 D3 89 05 [R_InterruptStatus] = r1 //
00009872 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009874 90 9A RETF
//////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_MS01_Initial:
// ...
// call F_SP_SACM_MS01_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
//////////////////////////////////////////////////////////////////
F_SP_SACM_MS01_Init_:
00009875 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
00009876 19 D3 13 70 [P_SystemClock] = r1; // Initial System Clock
00009878 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
00009879 19 D3 0B 70 [P_TimerA_Ctrl] = r1 // Initial Timer A
//R1 = 0x0003 // 8K
0000987B 40 92 r1 = 0x0000 // Fosc/2
0000987C 19 D3 0D 70 [P_TimerB_Ctrl] = r1; // Initial Timer B -> 8192
//R1 = 0xFFFF
0000987E 09 93 00 FA r1 = 0xFA00 // Any time for ADPCM channel 0,1
00009880 19 D3 0C 70 [P_TimerB_Data] = r1 // 8K sample rate
00009882 09 93 FF FF r1 = 0xffff
00009884 19 D3 11 70 [P_INT_Clear] = r1 // Clear interrupt occuiped events
00009886 90 9A RETF
//........................................
F_SP_PlayMode0_: // with F_SP_SACM_MS01_Initial
00009887 46 92 r1 = 0x0006
00009888 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000988A 09 93 00 FE r1 = 0xFE00
0000988C 19 D3 0A 70 [P_TimerA_Data] = r1 //
0000988E 11 93 89 05 r1 = [R_InterruptStatus] //
00009890 09 A3 10 84 r1 |= C_FIQ_PWM+C_IRQ2_TMB+C_IRQ4_1KHz
00009892 19 D3 89 05 [R_InterruptStatus] = r1 //
00009894 19 D3 10 70 [P_INT_Ctrl] = r1 //
00009896 90 9A RETF
F_SP_PlayMode1_: // with F_SP_SACM_MS01_Initial
00009897 09 93 A8 00 r1 = 0x00A8
00009899 19 D3 2A 70 [P_DAC_Ctrl] = r1
0000989B 09 93 00 FE r1 = 0xFE00
0000989D 19 D3 0A 70 [P_TimerA_Data] = r1 //
0000989F 11 93 89 05 r1 = [R_InterruptStatus] //
000098A1 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000098A3 19 D3 89 05 [R_InterruptStatus] = r1 //
000098A5 19 D3 10 70 [P_INT_Ctrl] = r1 //
000098A7 90 9A RETF
F_SP_PlayMode2_: // with F_SP_SACM_MS01_Initial
000098A8 09 93 A8 00 r1 = 0x00A8
000098AA 19 D3 2A 70 [P_DAC_Ctrl] = r1
000098AC 09 93 9A FD r1 = 0xFD9A
000098AE 19 D3 0A 70 [P_TimerA_Data] = r1 //
000098B0 11 93 89 05 r1 = [R_InterruptStatus] //
000098B2 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000098B4 19 D3 89 05 [R_InterruptStatus] = r1 //
000098B6 19 D3 10 70 [P_INT_Ctrl] = r1 //
000098B8 90 9A RETF
F_SP_PlayMode3_: // with F_SP_SACM_MS01_Initial
000098B9 09 93 A8 00 r1 = 0x00A8
000098BB 19 D3 2A 70 [P_DAC_Ctrl] = r1
000098BD 09 93 00 FD r1 = 0xFD00
000098BF 19 D3 0A 70 [P_TimerA_Data] = r1 //
000098C1 11 93 89 05 r1 = [R_InterruptStatus] //
000098C3 09 A3 10 24 r1 |= C_FIQ_TMA+C_IRQ2_TMB+C_IRQ4_1KHz
000098C5 19 D3 89 05 [R_InterruptStatus] = r1 //
000098C7 19 D3 10 70 [P_INT_Ctrl] = r1 //
000098C9 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_MS01_Initial()
// or F_SACM_MS01_Initial:
//
// Ex: F_SACM_DVR_Initial:
// ...
// call F_SP_SACM_DVR_Init_
// call F_SP_Play_Mode0/1/2/3 ->0,1,2,3 depending on the para1
// ...
// retf
// Ex1:
// F_SACM_DVR_Record: (or F_SACM_DVR_InitEncoder)
// ...
// call F_SP_SACM_DVR_Rec_Init
// ...
// retf
// Ex2:
// F_SACM_DVR_Play: (or F_SACM_DVR_InitDecoder)
// ...
// call F_SP_SACM_DVR_Play_Init_
// ...
// retf
///////////////////////////////////////////////////////////////////////////////
F_SP_SACM_DVR_Init_:
000098CA 40 92 r1 = 0x0000; // 24MHz, Fcpu=Fosc
000098CB 19 D3 13 70 [P_SystemClock] = r1; // Frequency 20MHz
000098CD 70 92 r1 = 0x0030; // TimerA CKA=Fosc/2 CKB=1 Tout:off
000098CE 19 D3 0B 70 [P_TimerA_Ctrl] = r1;
000098D0 09 93 00 FA r1 = 0xfa00; // 8K @ 24.576MHz
//r1 = 0xfb1d; // 8K @ 20MHz
000098D2 19 D3 0A 70 [P_TimerA_Data] = r1;
000098D4 75 92 r1 = 0x0035; // ADINI should be open (107)
000098D5 19 D3 15 70 [P_ADC_Ctrl] = r1;
000098D7 09 93 A8 00 r1 = 0x00A8; // Set the DA Ctrl
000098D9 19 D3 2A 70 [P_DAC_Ctrl] = r1;
000098DB 09 93 FF FF r1 = 0xffff;
000098DD 19 D3 11 70 [P_INT_Clear] = r1; // Clear interrupt occuiped events
000098DF 11 93 89 05 r1 = [R_InterruptStatus] //
000098E1 09 A3 00 20 r1 |= C_FIQ_TMA // Enable Timer A FIQ
000098E3 19 D3 89 05 [R_InterruptStatus] = r1 //
000098E5 19 D3 10 70 [P_INT_Ctrl] = r1 //
000098E7 90 9A RETF
F_SP_SACM_DVR_Rec_Init_: // call by SACM_DVR_Record / SACM_DVR_InitEncoder
000098E8 75 92 r1 = 0x0035; //mic input
//r1 = 0x0037 //line_in input
000098E9 19 D3 15 70 [P_ADC_Ctrl] = r1; //enable ADC
000098EB 09 93 00 FE r1=0xfe00; //24K @ 24.576MHz
000098ED 19 D3 0A 70 [P_TimerA_Data] = r1
000098EF 90 9A RETF
F_SP_SACM_DVR_Play_Init_:
000098F0 40 92 r1 = 0x0000 // call by SACM_DVR_Stop / SACM_DVR_Play
000098F1 19 D3 15 70 [P_ADC_Ctrl] = r1; // Disable ADC
000098F3 09 93 00 FD r1 = 0xfd00; // 16K @ 24.576MHz
000098F5 19 D3 0A 70 [P_TimerA_Data] = r1;
000098F7 90 9A RETF
///////////////////////////////////////////////////////////////////////////////
// Function: Extra Functions provided by Sunplus
// Type:
// 1. DAC Ramp up/down
// 2. IO config/import/export
// 3. Get resource data
//
//
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Function: Ramp Up/Down to avoid speaker "pow" noise
// Destory: R1,R2
////////////////////////////////////////////////////////
_SP_RampUpDAC1: .PROC
F_SP_RampUpDAC1:
000098F8 90 D4 push r1,r2 to [sp]
000098F9 11 93 17 70 r1=[P_DAC1]
000098FB 09 B3 C0 FF r1 &= ~0x003f
000098FD 09 43 00 80 cmp r1,0x8000
000098FF 0E 0E jb L_RU_NormalUp
00009900 19 5E je L_RU_End
L_RU_DownLoop:
00009901 40 F0 64 99 call F_Delay
00009903 41 94 r2 = 0x0001
00009904 1A D5 12 70 [P_Watchdog_Clear] = r2
00009906 09 23 40 00 r1 -= 0x40
00009908 19 D3 17 70 [P_DAC1] = r1
0000990A 09 43 00 80 cmp r1,0x8000
0000990C 4C 4E jne L_RU_DownLoop
L_RD_DownEnd:
0000990D 0C EE jmp L_RU_End
L_RU_NormalUp:
L_RU_Loop:
0000990E 40 F0 64 99 call F_Delay
00009910 41 94 r2 = 0x0001
00009911 1A D5 12 70 [P_Watchdog_Clear] = r2
00009913 09 03 40 00 r1 += 0x40
00009915 19 D3 17 70 [P_DAC1] = r1
00009917 09 43 00 80 cmp r1, 0x8000
00009919 4C 4E jne L_RU_Loop
L_RU_End:
0000991A 90 90 pop r1,r2 from [sp]
0000991B 90 9A retf
.ENDP
//............................................................
_SP_RampDnDAC1: .PROC
F_SP_RampDnDAC1:
0000991C 90 D4 push r1,r2 to [sp]
//int off
0000991D 11 93 17 70 r1 = [P_DAC1]
0000991F 09 B3 C0 FF r1 &= ~0x003F
00009921 0A 5E jz L_RD_End
L_RD_Loop:
00009922 40 F0 64 99 call F_Delay
00009924 41 94 r2 = 0x0001
00009925 1A D5 12 70 [P_Watchdog_Clear] = r2
00009927 09 23 40 00 r1 -= 0x40
00009929 19 D3 17 70 [P_DAC1] = r1
0000992B 4A 4E jnz L_RD_Loop
L_RD_End:
//int fiq,irq
0000992C 90 90 pop r1,r2 from [sp]
0000992D 90 9A retf
.ENDP
//..............................................................
_SP_RampUpDAC2: .PROC
F_SP_RampUpDAC2:
0000992E 90 D4 push r1,r2 to [sp]
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