register_16bits.vhd

simple MIPS source code very simple it has not complete but you can test it

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:23:01 04/02/2009 
-- Design Name: 
-- Module Name:    register_16bits - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity register_16bits is
Port (
	clk, we 		: in std_logic;
	reset 		: in std_logic;
	indata  		: in std_logic_vector( 15 downto 0);
	outdata 		: out std_logic_vector(15 downto 0)
);
end register_16bits;

architecture Behavioral of register_16bits is
signal data : std_logic_vector(15 downto 0);

begin
process(clk, reset, we , indata)
begin
	if reset = '0' then
		data <= (others => '0');
	elsif rising_edge(clk) then
		if we ='1' then
			data <= indata;
		else
			data <= data;
		end if;
	end if;
end process;

outdata <= data;

end Behavioral;