mux_16_to_1.vhd

simple MIPS source code very simple it has not complete but you can test it

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:28:58 04/02/2009 
-- Design Name: 
-- Module Name:    mux_16_to_1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_16_to_1 is
port(
	data00 	: in std_logic_vector(15 downto 0);
	data01	: in std_logic_vector(15 downto 0);
	data02	: in std_logic_vector(15 downto 0);
	data03	: in std_logic_vector(15 downto 0);
	data04 	: in std_logic_vector(15 downto 0);
	data05	: in std_logic_vector(15 downto 0);
	data06	: in std_logic_vector(15 downto 0);
	data07	: in std_logic_vector(15 downto 0);
	data08 	: in std_logic_vector(15 downto 0);
	data09	: in std_logic_vector(15 downto 0);
	data10	: in std_logic_vector(15 downto 0);
	data11	: in std_logic_vector(15 downto 0);
	data12 	: in std_logic_vector(15 downto 0);
	data13	: in std_logic_vector(15 downto 0);
	data14	: in std_logic_vector(15 downto 0);
	data15	: in std_logic_vector(15 downto 0);	
	sel		: in std_logic_vector(4 downto 0);
	outdata 	:out std_logic_vector(15 downto 0)
);
end mux_16_to_1;

architecture Behavioral of mux_16_to_1 is

begin
process ( data00, data01, data02, data03, sel)
	begin
		case sel is
			when "00000" 	=> outdata <= data00;
			when "00001" 	=> outdata <= data01;
			when "00010" 	=> outdata <= data02;
			when "00011" 	=> outdata <= data03;
			when "00100" 	=> outdata <= data04;
			when "00101" 	=> outdata <= data05;
			when "00110" 	=> outdata <= data06;
			when "00111" 	=> outdata <= data07;
			when "01000" 	=> outdata <= data08;
			when "01001" 	=> outdata <= data09;
			when "01010" 	=> outdata <= data10;
			when "01011" 	=> outdata <= data11;
			when "01100" 	=> outdata <= data12;
			when "01101" 	=> outdata <= data13;
			when "01110" 	=> outdata <= data14;
			when others => outdata <= data15;
		end case;
	end process;
end Behavioral;