op_and.vhd

simple MIPS source code very simple it has not complete but you can test it

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-- Company: 
-- Engineer: 
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-- Create Date:    11:13:53 04/04/2009 
-- Design Name: 
-- Module Name:    op_and - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity op_and is
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_and : out std_logic_vector(15 downto 0));
end op_and;

architecture Behavioral of op_and is
signal data : std_logic_vector(15 downto 0);
begin
	process (input1, input2, data)
	begin
		data <= input1 and input2;
	end process;
	
	output_from_and <= data;
	


end Behavioral;