📄 test_register.tbw
字号:
version 3
C:/Documents and Settings/alu_class/regisster_set.vhd
regisster_set
VHDL
VHDL
C:/Documents and Settings/alu_class/test_register.xwv
Clocked
-
-
10000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
15000000
15000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
data
clk
read_data1
clk
read_data2
clk
read_sel1
clk
read_sel2
clk
reset
clk
we
clk
write_sel1
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
read_data1_DIFF
read_data2_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
reset
we
data
read_sel1
read_sel2
write_sel1
read_data1
read_data2
SIGNAL_ORDER_END
DIFFERENTIAL_CLKS_BEGIN
DIFFERENTIAL_CLKS_END
DIVIDERS_BEGIN
DIVIDERS_END
SIGPROPS_BEGIN
SIGPROPS_END
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