top.vhd

simple MIPS source code very simple it has not complete but you can test it

-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:00:30 04/04/2009 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
port (
	clk			: in std_logic;
	reset			: in std_logic;	
	read_sel1	: in std_logic_vector(4 downto 0);
	read_sel2	: in std_logic_vector(4 downto 0);
	write_sel1	: in std_logic_vector(4 downto 0);
	we				: in std_logic;
	alu_sel		: in std_logic_vector(2 downto 0);
	data			: in std_logic_vector(15 downto 0);
	final_output: out std_logic_vector(15 downto 0)	
);
		
end top;

architecture Behavioral of top is

component regisster_set
port(
	clk			: in std_logic;
	reset			: in std_logic;
	data			: in std_logic_vector(15 downto 0);
	read_sel1	: in std_logic_vector(4 downto 0);
	read_sel2	: in std_logic_vector(4 downto 0);
	write_sel1	: in std_logic_vector(4 downto 0);
	we				: in std_logic;
	read_data1	: out std_logic_vector(15 downto 0);
	read_data2	: out std_logic_vector(15 downto 0));
end component;

component alu_module
port (
		sel : in std_logic_vector(2 downto 0);
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		outdata : out std_logic_vector(15 downto 0));
end component;

signal read_data1	: std_logic_vector(15 downto 0);
signal read_data2	: std_logic_vector(15 downto 0);
signal databack : std_logic_vector(15 downto 0);

begin

regi_set : regisster_set port map (
	clk => clk,
	reset => reset,
	data => databack,
	read_sel1 => read_sel1,
	read_sel2 => read_sel2,
	write_sel1 => write_sel1,
	we => we,
	read_data1 => read_data1,
	read_data2 => read_data2);
	
alu_mo : alu_module port map (
	sel => alu_sel,
	input1 => read_data1,
	input2 => read_data2,
	outdata => databack);

final_output <= databack;

end Behavioral;