op_xor.vhd

来自「simple MIPS source code very simple it h」· VHDL 代码 · 共 52 行

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-- Company: 
-- Engineer: 
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-- Create Date:    11:15:47 04/04/2009 
-- Design Name: 
-- Module Name:    op_xor - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity op_xor is
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_xor : out std_logic_vector(15 downto 0));

end op_xor;

architecture Behavioral of op_xor is
signal data : std_logic_vector(15 downto 0);

begin
	process (input1, input2, data)
	begin
		data <= input1 xor input2;
	end process;
	
	output_from_xor <= data;


end Behavioral;