📄 test_register.ant
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.2i
-- \ \ Application : ISE
-- / / Filename : test_register.ant
-- /___/ /\ Timestamp : Thu Apr 02 13:06:18 2009
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: test_register
--Device: Xilinx
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY test_register IS
END test_register;
ARCHITECTURE testbench_arch OF test_register IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "C:\Documents and Settings\alu_class\test_register.ano";
COMPONENT regisster_set
PORT (
clk : In std_logic;
reset : In std_logic;
data : In std_logic_vector (15 DownTo 0);
read_sel1 : In std_logic_vector (1 DownTo 0);
read_sel2 : In std_logic_vector (1 DownTo 0);
write_sel1 : In std_logic_vector (1 DownTo 0);
we : In std_logic;
read_data1 : Out std_logic_vector (15 DownTo 0);
read_data2 : Out std_logic_vector (15 DownTo 0)
);
END COMPONENT;
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL data : std_logic_vector (15 DownTo 0) := "0000000000000000";
SIGNAL read_sel1 : std_logic_vector (1 DownTo 0) := "00";
SIGNAL read_sel2 : std_logic_vector (1 DownTo 0) := "00";
SIGNAL write_sel1 : std_logic_vector (1 DownTo 0) := "00";
SIGNAL we : std_logic := '0';
SIGNAL read_data1 : std_logic_vector (15 DownTo 0) := "0000000000000000";
SIGNAL read_data2 : std_logic_vector (15 DownTo 0) := "0000000000000000";
SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;
constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 ns;
BEGIN
UUT : regisster_set
PORT MAP (
clk => clk,
reset => reset,
data => data,
read_sel1 => read_sel1,
read_sel2 => read_sel2,
write_sel1 => write_sel1,
we => we,
read_data1 => read_data1,
read_data2 => read_data2
);
PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Annotation process for clk
VARIABLE TX_TIME : INTEGER := 0;
PROCEDURE ANNOTATE_read_data1(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", read_data1, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, read_data1);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
PROCEDURE ANNOTATE_read_data2(
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
STD.TEXTIO.write(TX_LOC, string'("Annotate["));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'(", read_data2, "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, read_data2);
STD.TEXTIO.write(TX_LOC, string'("]"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
END;
BEGIN
WAIT for 1 fs;
ANNOTATE_read_data1(0);
ANNOTATE_read_data2(0);
WAIT for OFFSET;
TX_TIME := TX_TIME + 100;
ANNO_LOOP : LOOP
--Rising Edge
WAIT for 115 ns;
TX_TIME := TX_TIME + 115;
ANNOTATE_read_data1(TX_TIME);
ANNOTATE_read_data2(TX_TIME);
WAIT for 85 ns;
TX_TIME := TX_TIME + 85;
END LOOP ANNO_LOOP;
END PROCESS;
PROCESS
BEGIN
-- ------------- Current Time: 185ns
WAIT FOR 185 ns;
reset <= '1';
data <= "0000001000000000";
-- -------------------------------------
-- ------------- Current Time: 985ns
WAIT FOR 800 ns;
write_sel1 <= "01";
-- -------------------------------------
-- ------------- Current Time: 1185ns
WAIT FOR 200 ns;
write_sel1 <= "10";
-- -------------------------------------
-- ------------- Current Time: 1385ns
WAIT FOR 200 ns;
write_sel1 <= "11";
-- -------------------------------------
-- ------------- Current Time: 1585ns
WAIT FOR 200 ns;
write_sel1 <= "00";
-- -------------------------------------
-- ------------- Current Time: 1985ns
WAIT FOR 400 ns;
read_sel2 <= "01";
-- -------------------------------------
-- ------------- Current Time: 2185ns
WAIT FOR 200 ns;
read_sel2 <= "10";
-- -------------------------------------
-- ------------- Current Time: 2385ns
WAIT FOR 200 ns;
read_sel2 <= "11";
-- -------------------------------------
-- ------------- Current Time: 2585ns
WAIT FOR 200 ns;
read_sel2 <= "00";
-- -------------------------------------
-- ------------- Current Time: 2785ns
WAIT FOR 200 ns;
we <= '1';
read_sel1 <= "01";
-- -------------------------------------
-- ------------- Current Time: 2985ns
WAIT FOR 200 ns;
read_sel1 <= "10";
-- -------------------------------------
-- ------------- Current Time: 3185ns
WAIT FOR 200 ns;
read_sel1 <= "11";
-- -------------------------------------
-- ------------- Current Time: 3385ns
WAIT FOR 200 ns;
read_sel1 <= "00";
-- -------------------------------------
-- ------------- Current Time: 3585ns
WAIT FOR 200 ns;
write_sel1 <= "01";
-- -------------------------------------
-- ------------- Current Time: 3785ns
WAIT FOR 200 ns;
write_sel1 <= "10";
-- -------------------------------------
-- ------------- Current Time: 3985ns
WAIT FOR 200 ns;
write_sel1 <= "11";
-- -------------------------------------
-- ------------- Current Time: 4185ns
WAIT FOR 200 ns;
we <= '0';
write_sel1 <= "00";
-- -------------------------------------
-- ------------- Current Time: 5185ns
WAIT FOR 1000 ns;
read_sel2 <= "01";
-- -------------------------------------
-- ------------- Current Time: 5385ns
WAIT FOR 200 ns;
read_sel2 <= "10";
-- -------------------------------------
-- ------------- Current Time: 5585ns
WAIT FOR 200 ns;
read_sel2 <= "11";
-- -------------------------------------
-- ------------- Current Time: 5785ns
WAIT FOR 200 ns;
read_sel2 <= "00";
-- -------------------------------------
-- ------------- Current Time: 6185ns
WAIT FOR 400 ns;
read_sel1 <= "01";
-- -------------------------------------
-- ------------- Current Time: 6385ns
WAIT FOR 200 ns;
read_sel1 <= "10";
-- -------------------------------------
-- ------------- Current Time: 6585ns
WAIT FOR 200 ns;
read_sel1 <= "11";
-- -------------------------------------
-- ------------- Current Time: 6785ns
WAIT FOR 200 ns;
read_sel1 <= "00";
-- -------------------------------------
WAIT FOR 3415 ns;
STD.TEXTIO.write(TX_OUT, string'("Total[]"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Success! Simulation for annotation completed"
SEVERITY FAILURE;
END PROCESS;
END testbench_arch;
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