op_mux.vhd

来自「simple MIPS source code very simple it h」· VHDL 代码 · 共 60 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:50:54 04/04/2009 
-- Design Name: 
-- Module Name:    op_mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity op_mux is
port (
		sel : in std_logic_vector(2 downto 0);
		data_from_add : in std_logic_vector(15 downto 0);
		data_from_sub : in std_logic_vector(15 downto 0);
		data_from_and : in std_logic_vector(15 downto 0);
		data_from_or : in std_logic_vector(15 downto 0);
		data_from_xor : in std_logic_vector(15 downto 0);
		outdata : out std_logic_vector(15 downto 0));
	
end op_mux;

architecture Behavioral of op_mux is
signal data : std_logic_vector(15 downto 0);
begin
	process(sel, data_from_add, data_from_sub, data_from_and, data_from_or, data_from_xor)
	begin
		case sel is
			when "000" =>	data <= data_from_add;
			when "001" =>	data <= data_from_sub;
			when "010" =>	data <= data_from_and;
			when "011" =>	data <= data_from_or;
			when others =>	data <= data_from_xor;
		end case;
	end process;
	
	outdata <= data;

end Behavioral;