ftytfty.vhw

simple MIPS source code very simple it has not complete but you can test it

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : ISE
--  /   /         Filename : ftytfty.vhw
-- /___/   /\     Timestamp : Sat Apr 04 10:19:00 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: ftytfty
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ftytfty IS
END ftytfty;

ARCHITECTURE testbench_arch OF ftytfty IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

    COMPONENT regisster_set
        PORT (
            clk : In std_logic;
            reset : In std_logic;
            data : In std_logic_vector (15 DownTo 0);
            read_sel1 : In std_logic_vector (1 DownTo 0);
            read_sel2 : In std_logic_vector (1 DownTo 0);
            write_sel1 : In std_logic_vector (1 DownTo 0);
            we : In std_logic;
            read_data1 : Out std_logic_vector (15 DownTo 0);
            read_data2 : Out std_logic_vector (15 DownTo 0)
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL data : std_logic_vector (15 DownTo 0) := "0000000000000000";
    SIGNAL read_sel1 : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL read_sel2 : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL write_sel1 : std_logic_vector (1 DownTo 0) := "00";
    SIGNAL we : std_logic := '0';
    SIGNAL read_data1 : std_logic_vector (15 DownTo 0) := "0000000000000000";
    SIGNAL read_data2 : std_logic_vector (15 DownTo 0) := "0000000000000000";

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;

    BEGIN
        UUT : regisster_set
        PORT MAP (
            clk => clk,
            reset => reset,
            data => data,
            read_sel1 => read_sel1,
            read_sel2 => read_sel2,
            write_sel1 => write_sel1,
            we => we,
            read_data1 => read_data1,
            read_data2 => read_data2
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  100ns
                WAIT FOR 100 ns;
                data <= "0000001000010000";
                -- -------------------------------------
                -- -------------  Current Time:  385ns
                WAIT FOR 285 ns;
                reset <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  785ns
                WAIT FOR 400 ns;
                we <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  985ns
                WAIT FOR 200 ns;
                read_sel1 <= "11";
                -- -------------------------------------
                -- -------------  Current Time:  1185ns
                WAIT FOR 200 ns;
                we <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  1385ns
                WAIT FOR 200 ns;
                read_sel1 <= "00";
                -- -------------------------------------
                -- -------------  Current Time:  1985ns
                WAIT FOR 600 ns;
                we <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  2185ns
                WAIT FOR 200 ns;
                write_sel1 <= "10";
                -- -------------------------------------
                -- -------------  Current Time:  2385ns
                WAIT FOR 200 ns;
                we <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  2585ns
                WAIT FOR 200 ns;
                write_sel1 <= "00";
                -- -------------------------------------
                -- -------------  Current Time:  3185ns
                WAIT FOR 600 ns;
                read_sel1 <= "01";
                -- -------------------------------------
                -- -------------  Current Time:  3985ns
                WAIT FOR 800 ns;
                read_sel1 <= "00";
                -- -------------------------------------
                -- -------------  Current Time:  4785ns
                WAIT FOR 800 ns;
                read_sel2 <= "10";
                -- -------------------------------------
                -- -------------  Current Time:  5385ns
                WAIT FOR 600 ns;
                read_sel1 <= "10";
                -- -------------------------------------
                WAIT FOR 4815 ns;

            END PROCESS;

    END testbench_arch;