regisster_set.vhd

simple MIPS source code very simple it has not complete but you can test it

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:41:59 04/02/2009 
-- Design Name: 
-- Module Name:    regisster_set - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity regisster_set is
port(
	clk			: in std_logic;
	reset			: in std_logic;
	data			: in std_logic_vector(15 downto 0);
	read_sel1	: in std_logic_vector(4 downto 0);
	read_sel2	: in std_logic_vector(4 downto 0);
	write_sel1	: in std_logic_vector(4 downto 0);
	we				: in std_logic;
	read_data1	: out std_logic_vector(15 downto 0);
	read_data2	: out std_logic_vector(15 downto 0)
);
end regisster_set;

architecture Behavioral of regisster_set is
signal we00 : std_logic;
signal we01 : std_logic;
signal we02 : std_logic;
signal we03 : std_logic;
signal we04 : std_logic;
signal we05 : std_logic;
signal we06 : std_logic;
signal we07 : std_logic;
signal we08 : std_logic;
signal we09 : std_logic;
signal we10 : std_logic;
signal we11 : std_logic;
signal we12 : std_logic;
signal we13 : std_logic;
signal we14 : std_logic;
signal we15 : std_logic;

signal data00 : std_logic_vector(15 downto 0);
signal data01 : std_logic_vector(15 downto 0);
signal data02 : std_logic_vector(15 downto 0);
signal data03 : std_logic_vector(15 downto 0);
signal data04 : std_logic_vector(15 downto 0);
signal data05 : std_logic_vector(15 downto 0);
signal data06 : std_logic_vector(15 downto 0);
signal data07 : std_logic_vector(15 downto 0);
signal data08 : std_logic_vector(15 downto 0);
signal data09 : std_logic_vector(15 downto 0);
signal data10 : std_logic_vector(15 downto 0);
signal data11 : std_logic_vector(15 downto 0);
signal data12 : std_logic_vector(15 downto 0);
signal data13 : std_logic_vector(15 downto 0);
signal data14 : std_logic_vector(15 downto 0);
signal data15 : std_logic_vector(15 downto 0);

component register_16bits 
Port (
	clk, we 		: in std_logic;
	reset 		: in std_logic;
	indata  		: in std_logic_vector( 15 downto 0);
	outdata 		: out std_logic_vector(15 downto 0)
);
end component;

component mux_16_to_1 
port(
	data00 	: in std_logic_vector(15 downto 0);
	data01	: in std_logic_vector(15 downto 0);
	data02	: in std_logic_vector(15 downto 0);
	data03	: in std_logic_vector(15 downto 0);
	data04 	: in std_logic_vector(15 downto 0);
	data05	: in std_logic_vector(15 downto 0);
	data06	: in std_logic_vector(15 downto 0);
	data07	: in std_logic_vector(15 downto 0);
	data08 	: in std_logic_vector(15 downto 0);
	data09	: in std_logic_vector(15 downto 0);
	data10	: in std_logic_vector(15 downto 0);
	data11	: in std_logic_vector(15 downto 0);
	data12 	: in std_logic_vector(15 downto 0);
	data13	: in std_logic_vector(15 downto 0);
	data14	: in std_logic_vector(15 downto 0);
	data15	: in std_logic_vector(15 downto 0);	
	sel		: in std_logic_vector(4 downto 0);
	outdata 	:out std_logic_vector(15 downto 0)
);
end component;

component demux_1_to_16 
port(
	we 			: in std_logic;
	sel			: in std_logic_vector(4 downto 0);
	data_en00	: out std_logic;
	data_en01	: out std_logic;
	data_en02	: out std_logic;
	data_en03	: out std_logic;
	data_en04	: out std_logic;
	data_en05	: out std_logic;
	data_en06	: out std_logic;
	data_en07	: out std_logic;
	data_en08	: out std_logic;
	data_en09	: out std_logic;
	data_en10	: out std_logic;
	data_en11	: out std_logic;
	data_en12	: out std_logic;
	data_en13	: out std_logic;
	data_en14	: out std_logic;
	data_en15	: out std_logic
);
end component;
 
begin

reg00 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we00,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data00
);

reg01 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we01,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data01
);


reg02 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we02,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data02
);

reg03 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we03,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data03
);

reg04 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we04,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data04
);

reg05 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we05,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data05
);

reg06 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we06,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data06
);

reg07 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we07,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data07
);

reg08 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we08,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data08
);

reg09 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we09,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data09
);

reg10 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we10,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data10
);

reg11 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we11,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data11
);

reg12 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we12,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data12
);

reg13 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we13,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data13
);

reg14 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we14,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data14
);

reg15 : register_16bits 
Port map (
	clk			=> clk,
	we		 		=> we15,
	reset 		=> reset,
	indata  		=> data,
	outdata 		=> data15
);


mux1 : mux_16_to_1 
port map(
	data00 => data00, 	
	data01 => data01,
	data02 => data02,
	data03 => data03,
	data04 => data04, 	
	data05 => data05,
	data06 => data06,
	data07 => data07,
	data08 => data08, 	
	data09 => data09,
	data10 => data10,
	data11 => data11,
	data12 => data12, 	
	data13 => data13,
	data14 => data14,
	data15 => data15,	
	sel	 => read_sel1,	
	outdata => read_data1
);

mux2 : mux_16_to_1 
port map(
	data00 => data00, 	
	data01 => data01,
	data02 => data02,
	data03 => data03,
	data04 => data04, 	
	data05 => data05,
	data06 => data06,
	data07 => data07,
	data08 => data08, 	
	data09 => data09,
	data10 => data10,
	data11 => data11,
	data12 => data12, 	
	data13 => data13,
	data14 => data14,
	data15 => data15,	
	sel	 => read_sel2,	
	outdata => read_data2
);

demux : demux_1_to_16 
port map(
	we 		 => we,
	sel		 => write_sel1,
	data_en00 => we00,
	data_en01 => we01,
	data_en02 => we02,
	data_en03 => we03,
	data_en04 => we04,
	data_en05 => we05,
	data_en06 => we06,
	data_en07 => we07,
	data_en08 => we08,
	data_en09 => we09,
	data_en10 => we10,
	data_en11 => we11,
	data_en12 => we12,
	data_en13 => we13,
	data_en14 => we14,
	data_en15 => we15
);

end Behavioral;