alu_module.vhd

simple MIPS source code very simple it has not complete but you can test it

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:54:28 04/04/2009 
-- Design Name: 
-- Module Name:    alu_module - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu_module is
port (
		sel : in std_logic_vector(2 downto 0);
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);		
		outdata : out std_logic_vector(15 downto 0));
end alu_module;

architecture Behavioral of alu_module is

component op_mux 
port (
		sel : in std_logic_vector(2 downto 0);
		data_from_add : in std_logic_vector(15 downto 0);
		data_from_sub : in std_logic_vector(15 downto 0);
		outdata : out std_logic_vector(15 downto 0));
end component;

component op_add
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_add : out std_logic_vector(15 downto 0));
end component;

component op_sub
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_sub : out std_logic_vector(15 downto 0));
end component;	

component op_and
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_and : out std_logic_vector(15 downto 0));
end component;	

component op_or
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_or : out std_logic_vector(15 downto 0));
end component;	

component op_xor
port (
		input1 : in std_logic_vector(15 downto 0);
		input2 : in std_logic_vector(15 downto 0);
		output_from_xor : out std_logic_vector(15 downto 0));
end component;	

signal data_from_add : std_logic_vector(15 downto 0);
signal data_from_sub : std_logic_vector(15 downto 0);
signal data_from_and : std_logic_vector(15 downto 0);
signal data_from_or : std_logic_vector(15 downto 0);
signal data_from_xor : std_logic_vector(15 downto 0);

begin

alu_add : op_add port map (
	input1 => input1,
	input2 => input2,
	output_from_add => data_from_add);
	
alu_sub : op_sub port map (
	input1 => input1,
	input2 => input2,
	output_from_sub => data_from_sub);

alu_and : op_and port map (
	input1 => input1,
	input2 => input2,
	output_from_and => data_from_and);

alu_or : op_or port map (
	input1 => input1,
	input2 => input2,
	output_from_or => data_from_or);

alu_xor : op_xor port map (
	input1 => input1,
	input2 => input2,
	output_from_xor => data_from_xor);

alu_mux : op_mux port map (
	sel => sel,
	data_from_add => data_from_add,
	data_from_sub => data_from_sub,
	outdata => outdata);

end Behavioral;