top.syr

simple MIPS source code very simple it has not complete but you can test it

    Summary:
	inferred  16 D-type flip-flop(s).
Unit <register_16bits> synthesized.


Synthesizing Unit <mux_16_to_1>.
    Related source file is "C:/micro_temp/alu_class/mux_16_to_1.vhd".
Unit <mux_16_to_1> synthesized.


Synthesizing Unit <demux_1_to_16>.
    Related source file is "C:/micro_temp/alu_class/demux_1_to_16.vhd".
Unit <demux_1_to_16> synthesized.


Synthesizing Unit <op_add>.
    Related source file is "C:/micro_temp/alu_class/op_add.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 16-bit adder for signal <data>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <op_add> synthesized.


Synthesizing Unit <op_sub>.
    Related source file is "C:/micro_temp/alu_class/op_sub.vhd".
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
    Found 16-bit subtractor for signal <data>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <op_sub> synthesized.


Synthesizing Unit <op_and>.
    Related source file is "C:/micro_temp/alu_class/op_and.vhd".
Unit <op_and> synthesized.


Synthesizing Unit <op_or>.
    Related source file is "C:/micro_temp/alu_class/op_or.vhd".
Unit <op_or> synthesized.


Synthesizing Unit <op_xor>.
    Related source file is "C:/micro_temp/alu_class/op_xor.vhd".
    Found 16-bit xor2 for signal <data>.
Unit <op_xor> synthesized.


Synthesizing Unit <op_mux>.
    Related source file is "C:/micro_temp/alu_class/op_mux.vhd".
Unit <op_mux> synthesized.


Synthesizing Unit <regisster_set>.
    Related source file is "C:/micro_temp/alu_class/regisster_set.vhd".
Unit <regisster_set> synthesized.


Synthesizing Unit <alu_module>.
    Related source file is "C:/micro_temp/alu_class/alu_module.vhd".
WARNING:Xst:646 - Signal <data_from_and> is assigned but never used.
WARNING:Xst:646 - Signal <data_from_xor> is assigned but never used.
WARNING:Xst:646 - Signal <data_from_or> is assigned but never used.
Unit <alu_module> synthesized.


Synthesizing Unit <top>.
    Related source file is "C:/micro_temp/alu_class/top.vhd".
WARNING:Xst:647 - Input <data> is never used.
Unit <top> synthesized.

WARNING:Xst:524 - All outputs of the instance <alu_and> of the block <op_and> are unconnected in block <alu_module>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <alu_or> of the block <op_or> are unconnected in block <alu_module>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 16-bit adder                                          : 1
 16-bit subtractor                                     : 1
# Registers                                            : 16
 16-bit register                                       : 16
# Xors                                                 : 1
 16-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '2s50e.nph' in environment C:\Xilinx92i.
WARNING:Xst:1290 - Hierarchical block <alu_xor> is unconnected in block <alu_mo>.
   It will be removed from the design.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 16-bit adder                                          : 1
 16-bit subtractor                                     : 1
# Registers                                            : 256
 Flip-Flops                                            : 256
# Xors                                                 : 1
 16-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <regisster_set> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 34.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 256
 Flip-Flops                                            : 256

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 53

Cell Usage :
# BELS                             : 553
#      GND                         : 1
#      INV                         : 3
#      LUT2                        : 96
#      LUT3                        : 5
#      LUT4                        : 320
#      LUT4_L                      : 64
#      MUXCY                       : 30
#      MUXF5                       : 2
#      VCC                         : 1
#      XORCY                       : 31
# FlipFlops/Latches                : 256
#      FDCE                        : 256
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 36
#      IBUF                        : 20
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50eft256-7 

 Number of Slices:                     266  out of    768    34%  
 Number of Slice Flip Flops:           256  out of   1536    16%  
 Number of 4 input LUTs:               488  out of   1536    31%  
 Number of IOs:                         53
 Number of bonded IOBs:                 37  out of    178    20%  
 Number of GCLKs:                        1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.