top.syr

simple MIPS source code very simple it has not complete but you can test it

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.14 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.14 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc2s50e-7-ft256

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Convert Tristates To Logic         : Yes
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : top.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/micro_temp/alu_class/op_add.vhd" in Library work.
Architecture behavioral of Entity op_add is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/op_sub.vhd" in Library work.
Architecture behavioral of Entity op_sub is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/op_and.vhd" in Library work.
Architecture behavioral of Entity op_and is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/op_or.vhd" in Library work.
Architecture behavioral of Entity op_or is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/op_xor.vhd" in Library work.
Architecture behavioral of Entity op_xor is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/op_mux.vhd" in Library work.
Architecture behavioral of Entity op_mux is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/register_16bits.vhd" in Library work.
Architecture behavioral of Entity register_16bits is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/mux_16_to_1.vhd" in Library work.
Architecture behavioral of Entity mux_16_to_1 is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/demux_1_to_16.vhd" in Library work.
Architecture behavioral of Entity demux_1_to_16 is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/regisster_set.vhd" in Library work.
Architecture behavioral of Entity regisster_set is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/alu_module.vhd" in Library work.
Architecture behavioral of Entity alu_module is up to date.
Compiling vhdl file "C:/micro_temp/alu_class/top.vhd" in Library work.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <regisster_set> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <alu_module> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <register_16bits> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <mux_16_to_1> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <demux_1_to_16> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_add> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_sub> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_and> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_or> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_xor> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <op_mux> in library <work> (architecture <behavioral>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> in library <work> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <regisster_set> in library <work> (Architecture <behavioral>).
Entity <regisster_set> analyzed. Unit <regisster_set> generated.

Analyzing Entity <register_16bits> in library <work> (Architecture <behavioral>).
Entity <register_16bits> analyzed. Unit <register_16bits> generated.

Analyzing Entity <mux_16_to_1> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/micro_temp/alu_class/mux_16_to_1.vhd" line 56: The following signals are missing in the process sensitivity list:
   data04, data05, data06, data07, data08, data09, data10, data11, data12, data13, data14, data15.
Entity <mux_16_to_1> analyzed. Unit <mux_16_to_1> generated.

Analyzing Entity <demux_1_to_16> in library <work> (Architecture <behavioral>).
Entity <demux_1_to_16> analyzed. Unit <demux_1_to_16> generated.

Analyzing Entity <alu_module> in library <work> (Architecture <behavioral>).
WARNING:Xst:752 - "C:/micro_temp/alu_class/alu_module.vhd" line 116: Unconnected input port 'data_from_and' of component 'op_mux' is tied to default value.
WARNING:Xst:752 - "C:/micro_temp/alu_class/alu_module.vhd" line 116: Unconnected input port 'data_from_or' of component 'op_mux' is tied to default value.
WARNING:Xst:752 - "C:/micro_temp/alu_class/alu_module.vhd" line 116: Unconnected input port 'data_from_xor' of component 'op_mux' is tied to default value.
Entity <alu_module> analyzed. Unit <alu_module> generated.

Analyzing Entity <op_add> in library <work> (Architecture <behavioral>).
Entity <op_add> analyzed. Unit <op_add> generated.

Analyzing Entity <op_sub> in library <work> (Architecture <behavioral>).
Entity <op_sub> analyzed. Unit <op_sub> generated.

Analyzing Entity <op_and> in library <work> (Architecture <behavioral>).
Entity <op_and> analyzed. Unit <op_and> generated.

Analyzing Entity <op_or> in library <work> (Architecture <behavioral>).
Entity <op_or> analyzed. Unit <op_or> generated.

Analyzing Entity <op_xor> in library <work> (Architecture <behavioral>).
Entity <op_xor> analyzed. Unit <op_xor> generated.

Analyzing Entity <op_mux> in library <work> (Architecture <behavioral>).
Entity <op_mux> analyzed. Unit <op_mux> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <register_16bits>.
    Related source file is "C:/micro_temp/alu_class/register_16bits.vhd".
    Found 16-bit register for signal <data>.