pskfsk.fit.qmsg

it is a program of FSK AND PSK

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.30 1 10 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 1 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 4 18 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.834 ns register memory " "Info: Estimated most critical path is register to memory delay of 3.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT100\[0\] 1 REG LAB_X15_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y4; Fanout = 4; REG Node = 'COUNT100\[0\]'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "" { COUNT100[0] } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.575 ns) 1.279 ns add~309COUT1_382 2 COMB LAB_X16_Y4 2 " "Info: 2: + IC(0.704 ns) + CELL(0.575 ns) = 1.279 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~309COUT1_382'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "1.279 ns" { COUNT100[0] add~309COUT1_382 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.359 ns add~314COUT1_384 3 COMB LAB_X16_Y4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.359 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~314COUT1_384'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.080 ns" { add~309COUT1_382 add~314COUT1_384 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.439 ns add~319COUT1_385 4 COMB LAB_X16_Y4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.439 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~319COUT1_385'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.080 ns" { add~314COUT1_384 add~319COUT1_385 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.697 ns add~324 5 COMB LAB_X16_Y4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.697 ns; Loc. = LAB_X16_Y4; Fanout = 3; COMB Node = 'add~324'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.258 ns" { add~319COUT1_385 add~324 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.376 ns add~327 6 COMB LAB_X16_Y4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.376 ns; Loc. = LAB_X16_Y4; Fanout = 2; COMB Node = 'add~327'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.679 ns" { add~324 add~327 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.442 ns) 3.267 ns COUNT100~225 7 COMB LAB_X15_Y4 8 " "Info: 7: + IC(0.449 ns) + CELL(0.442 ns) = 3.267 ns; Loc. = LAB_X15_Y4; Fanout = 8; COMB Node = 'COUNT100~225'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.891 ns" { add~327 COUNT100~225 } "NODE_NAME" } "" } } { "PSKFSK.vhd" "" { Text "D:/QQQ/fskpsk1/PSKFSK.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.184 ns) + CELL(0.383 ns) 3.834 ns altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4 8 MEM M4K_X13_Y4 1 " "Info: 8: + IC(0.184 ns) + CELL(0.383 ns) = 3.834 ns; Loc. = M4K_X13_Y4; Fanout = 1; MEM Node = 'altsyncram:Mux_rtl_0\|altsyncram_36j:auto_generated\|ram_block1a0~porta_address_reg4'" {  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "0.567 ns" { COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } } { "db/altsyncram_36j.tdf" "" { Text "D:/QQQ/fskpsk1/db/altsyncram_36j.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.497 ns 65.13 % " "Info: Total cell delay = 2.497 ns ( 65.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.337 ns 34.87 % " "Info: Total interconnect delay = 1.337 ns ( 34.87 % )" {  } {  } 0}  } { { "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" "" { Report "D:/QQQ/fskpsk1/db/PSKFSK_cmp.qrpt" Compiler "PSKFSK" "UNKNOWN" "V1" "D:/QQQ/fskpsk1/db/PSKFSK.quartus_db" { Floorplan "D:/QQQ/fskpsk1/" "" "3.834 ns" { COUNT100[0] add~309COUT1_382 add~314COUT1_384 add~319COUT1_385 add~324 add~327 COUNT100~225 altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 02 11:54:14 2005 " "Info: Processing ended: Wed Nov 02 11:54:14 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}