pskfsk.tan.rpt

it is a program of FSK AND PSK

; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK           ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; MODE            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK'                                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------+-------------+------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From        ; To                                                                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 60.09 MHz ( period = 16.643 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.449 ns                ;
; N/A   ; 60.14 MHz ( period = 16.627 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.433 ns                ;
; N/A   ; 60.24 MHz ( period = 16.601 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.407 ns                ;
; N/A   ; 60.39 MHz ( period = 16.560 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.366 ns                ;
; N/A   ; 60.39 MHz ( period = 16.559 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.365 ns                ;
; N/A   ; 60.44 MHz ( period = 16.545 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.351 ns                ;
; N/A   ; 60.54 MHz ( period = 16.519 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.325 ns                ;
; N/A   ; 60.54 MHz ( period = 16.518 ns )               ; COUNT100[4] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.324 ns                ;
; N/A   ; 60.69 MHz ( period = 16.476 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.282 ns                ;
; N/A   ; 60.76 MHz ( period = 16.457 ns )               ; COUNT100[2] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.263 ns                ;
; N/A   ; 60.78 MHz ( period = 16.453 ns )               ; COUNT100[3] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.259 ns                ;
; N/A   ; 60.82 MHz ( period = 16.443 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.249 ns                ;
; N/A   ; 60.86 MHz ( period = 16.431 ns )               ; COUNT100[2] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.237 ns                ;
; N/A   ; 60.88 MHz ( period = 16.427 ns )               ; COUNT100[3] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.233 ns                ;
; N/A   ; 60.90 MHz ( period = 16.420 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.226 ns                ;
; N/A   ; 60.93 MHz ( period = 16.413 ns )               ; COUNT100[5] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg6 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.219 ns                ;
; N/A   ; 61.03 MHz ( period = 16.386 ns )               ; COUNT100[2] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.192 ns                ;
; N/A   ; 61.41 MHz ( period = 16.283 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg1 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.089 ns                ;
; N/A   ; 61.51 MHz ( period = 16.257 ns )               ; COUNT100[4] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.063 ns                ;
; N/A   ; 61.54 MHz ( period = 16.250 ns )               ; COUNT100[2] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.056 ns                ;
; N/A   ; 61.55 MHz ( period = 16.246 ns )               ; COUNT100[3] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 4.052 ns                ;
; N/A   ; 62.39 MHz ( period = 16.027 ns )               ; COUNT100[6] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg5 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 3.833 ns                ;
; N/A   ; 62.45 MHz ( period = 16.014 ns )               ; COUNT100[0] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg0 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 3.820 ns                ;
; N/A   ; 62.67 MHz ( period = 15.956 ns )               ; COUNT100[1] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg1 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 3.762 ns                ;
; N/A   ; 62.69 MHz ( period = 15.951 ns )               ; COUNT100[2] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 3.757 ns                ;
; N/A   ; 63.01 MHz ( period = 15.871 ns )               ; COUNT100[4] ; altsyncram:Mux_rtl_0|altsyncram_36j:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK      ; CLOCK    ; None                        ; None                      ; 3.677 ns                ;