arminit.c

skyeye的开源代码

			act.sa_handler = dbct_test_speed_sig;
			act.sa_flags = SA_RESTART;
			//cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF
#ifndef __CYGWIN__
			if (sigaction(SIGVTALRM, &act, NULL) == -1) {
#else
			if (sigaction(SIGALRM, &act, NULL) == -1) {
#endif	//__CYGWIN__
				fprintf(stderr, "init timer error.\n");
				skyeye_exit(-1);
			}
			if (skyeye_config.dbct_test_speed_sec) {
				value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec;
			}
			else {
				value.it_value.tv_sec = DBCT_TEST_SPEED_SEC;
			}
			printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec);
			value.it_value.tv_usec = 0;
			value.it_interval.tv_sec = 0; 
			value.it_interval.tv_usec = 0;
#ifndef __CYGWIN__
			if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) {
#else
			if (setitimer(ITIMER_REAL, &value, NULL) == -1) {
#endif	//__CYGWIN__
				fprintf(stderr, "init timer error.\n");
				skyeye_exit(-1);
			}
		}
	}
#endif	//DBCT_TEST_SPEED
//AJ2D--------------------------------------------------------------------------
	state->Emulate = RUN;
	while (state->Emulate != STOP) {
		state->Emulate = RUN;

		/*ywc 2005-03-31 */
		if (state->prog32Sig && ARMul_MODE32BIT) {
#ifndef NO_DBCT
			if (skyeye_config.no_dbct) {
				pc = ARMul_Emulate32 (state);
			}
			else {
				pc = ARMul_Emulate32_dbct (state);
			}
#else
			pc = ARMul_Emulate32 (state);
#endif
		}

		else
			pc = ARMul_Emulate26 (state);
		//chy 2006-02-22, should test debugmode first
		//chy 2006-04-14, put below codes in ARMul_Emulate
#if 0
		if(debugmode)
		  if(remote_interrupt())
			state->Emulate = STOP;
#endif
	}

	/*
	 * 2007-01-24 removed the term-io functions by Anthony Lee,
	 * moved to "device/uart/skyeye_uart_stdio.c".
	 */

	return (pc);
}

/***************************************************************************\
* Emulate the execution of one instruction.  Start the correct emulator     *
* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the   *
* address of the instruction that is executed.                              *
\***************************************************************************/

ARMword
ARMul_DoInstr (ARMul_State * state)
{
	ARMword pc = 0;

	state->Emulate = ONCE;

	/*ywc 2005-03-31 */
	if (state->prog32Sig && ARMul_MODE32BIT) {
#ifndef NO_DBCT
		if (skyeye_config.no_dbct) {
			pc = ARMul_Emulate32 (state);
		}
		else {
//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
#ifndef DBCT_GDBRSP
			printf("DBCT GDBRSP function switch is off.\n");
			printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n");
			skyeye_exit(-1);
#endif	//DBCT_GDBRSP
//AJ2D--------------------------------------------------------------------------
			pc = ARMul_Emulate32_dbct (state);
		}
#else
		pc = ARMul_Emulate32 (state);
#endif
	}

	else
		pc = ARMul_Emulate26 (state);

	return (pc);
}

/***************************************************************************\
* This routine causes an Abort to occur, including selecting the correct    *
* mode, register bank, and the saving of registers.  Call with the          *
* appropriate vector's memory address (0,4,8 ....)                          *
\***************************************************************************/

#if 0
void
ARMul_Abort (ARMul_State * state, ARMword vector)
{
	ARMword temp;

	state->Aborted = FALSE;

	if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
		return;

	if (state->prog32Sig)
		if (ARMul_MODE26BIT)
			temp = R15PC;
		else
			temp = state->Reg[15];
	else
		temp = R15PC | ECC | ER15INT | EMODE;

	switch (vector) {
	case ARMul_ResetV:	/* RESET */
		state->Spsr[SVCBANK] = CPSR;
		SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp;
		break;
	case ARMul_UndefinedInstrV:	/* Undefined Instruction */
		state->Spsr[state->prog32Sig ? UNDEFBANK : SVCBANK] = CPSR;
		SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	case ARMul_SWIV:	/* Software Interrupt */
		state->Spsr[SVCBANK] = CPSR;
		SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	case ARMul_PrefetchAbortV:	/* Prefetch Abort */
		state->AbortAddr = 1;
		state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR;
		SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	case ARMul_DataAbortV:	/* Data Abort */
		state->Spsr[state->prog32Sig ? ABORTBANK : SVCBANK] = CPSR;
		SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;	/* the PC must have been incremented */
		break;
	case ARMul_AddrExceptnV:	/* Address Exception */
		state->Spsr[SVCBANK] = CPSR;
		SETABORT (IBIT, SVC26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	case ARMul_IRQV:	/* IRQ */
		state->Spsr[IRQBANK] = CPSR;
		SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	case ARMul_FIQV:	/* FIQ */
		state->Spsr[FIQBANK] = CPSR;
		SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE);
		ARMul_CPSRAltered (state);
		state->Reg[14] = temp - 4;
		break;
	}
	if (ARMul_MODE32BIT) {
		if (state->mmu.control & CONTROL_VECTOR)
			vector += 0xffff0000;	//for v4 high exception  address
		ARMul_SetR15 (state, vector);
	}
	else
		ARMul_SetR15 (state, R15CCINTMODE | vector);
}
#endif

void
ARMul_Abort (ARMul_State * state, ARMword vector)
{
	ARMword temp;
	int isize = INSN_SIZE;
	int esize = (TFLAG ? 0 : 4);
	int e2size = (TFLAG ? -4 : 0);

	state->Aborted = FALSE;

	if (ARMul_OSException (state, vector, ARMul_GetPC (state)))
		return;

	if (state->prog32Sig)
		if (ARMul_MODE26BIT)
			temp = R15PC;
		else
			temp = state->Reg[15];
	else
		temp = R15PC | ECC | ER15INT | EMODE;

	switch (vector) {
	case ARMul_ResetV:	/* RESET */
		SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE,
			  0);
		break;
	case ARMul_UndefinedInstrV:	/* Undefined Instruction */
		SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE,
			  isize);
		break;
	case ARMul_SWIV:	/* Software Interrupt */
		SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
			  isize);
		break;
	case ARMul_PrefetchAbortV:	/* Prefetch Abort */
		state->AbortAddr = 1;
		SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
			  esize);
		break;
	case ARMul_DataAbortV:	/* Data Abort */
		SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
			  e2size);
		break;
	case ARMul_AddrExceptnV:	/* Address Exception */
		SETABORT (IBIT, SVC26MODE, isize);
		break;
	case ARMul_IRQV:	/* IRQ */
		//chy 2003-09-02 the if sentence seems no use
#if 0
		if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
		    || (temp & ARMul_CP13_R0_IRQ))
#endif
			SETABORT (IBIT,
				  state->prog32Sig ? IRQ32MODE : IRQ26MODE,
				  esize);
		break;
	case ARMul_FIQV:	/* FIQ */
		//chy 2003-09-02 the if sentence seems no use
#if 0
		if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
		    || (temp & ARMul_CP13_R0_FIQ))
#endif
			SETABORT (INTBITS,
				  state->prog32Sig ? FIQ32MODE : FIQ26MODE,
				  esize);
		break;
	}
	if (ARMul_MODE32BIT) {
		if (state->mmu.control & CONTROL_VECTOR)
			vector += 0xffff0000;	//for v4 high exception  address
		if (state->vector_remap_flag)
			vector += state->vector_remap_addr; /* support some remap function in LPC processor */
		ARMul_SetR15 (state, vector);
	}
	else
		ARMul_SetR15 (state, R15CCINTMODE | vector);
#if 0
	if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) {
		/* No vector has been installed.  Rather than simulating whatever
		   random bits might happen to be at address 0x20 onwards we elect
		   to stop.  */
		switch (vector) {
		case ARMul_ResetV:
			state->EndCondition = RDIError_Reset;
			break;
		case ARMul_UndefinedInstrV:
			state->EndCondition = RDIError_UndefinedInstruction;
			break;
		case ARMul_SWIV:
			state->EndCondition = RDIError_SoftwareInterrupt;
			break;
		case ARMul_PrefetchAbortV:
			state->EndCondition = RDIError_PrefetchAbort;
			break;
		case ARMul_DataAbortV:
			state->EndCondition = RDIError_DataAbort;
			break;
		case ARMul_AddrExceptnV:
			state->EndCondition = RDIError_AddressException;
			break;
		case ARMul_IRQV:
			state->EndCondition = RDIError_IRQ;
			break;
		case ARMul_FIQV:
			state->EndCondition = RDIError_FIQ;
			break;
		default:
			break;
		}
		state->Emulate = FALSE;
	}
#endif
}