📄 flash_drv_amd.c
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/*******************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2004
*
*******************************************************************************/
/*******************************************************************************
*
* Filename:
* ---------
* flash_drv_AMD.c
*
* Project:
* --------
* FlashTool Download Agent
*
* Description:
* ------------
* This Module defines the AMD family flash driver.
*
* Author:
* -------
* Amos Hsu
*
*==============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
* $Revision: 1.15 $
* $Modtime: Jan 05 2006 17:42:06 $
* $Log: //mtkvs01/vmdata/flash_tool/archives/DA/SRC/flash_drv_AMD.c-arc $
*
* Rev 1.15 Jan 14 2006 00:18:18 mtk00539
* Re-org source code.
* Resolution for 159: [FlashTool v2.7.1015]
*
* Rev 1.14 Jan 04 2006 14:40:10 mtk00539
* Bug fixes:
* 1. [DA] Fix Spansion S71PLXXXN detection problem by reading CFI info.
* 2. [DA] Fix TOSHIBA NAND flash callback function set, because TOSHIBA NAND flash doesn't support CopyBack command.
*
* New features:
* 1. [DA] Supports Spansion MirrorBit Buffer-Program method.
* 2. [DA] Supports new NOR flash device.
* [SPANSION] S71PL129N
*
* Enhancements:
* 1. [DA] Halt program when external RAM is less than 128KB.
* Resolution for 158: [FlashTool v2.7.1014][New] Support Spansion MirrorBit Buffer-Program method.
*
* Rev 1.13 Jan 02 2006 13:16:34 mtk00539
* Add new flash [SPANSION] S71PL256NC0HAW5B
* Resolution for 156: [FlashTool v2.7.1013][BUG FIX] Fix BootROM start command failure while manually selecting NMT6226 or MT6227 baseband chip.
*
* Rev 1.12 Dec 29 2005 10:51:18 mtk00539
* 1. [DA] Supports new NOR flash device.
* [SPANSION] S71PL127N
* [SILICON7] SV6D2832UTA
* [SILICON7] SV6D2832UBA
* [SILICON7] SV6C2832UTA
* [SILICON7] SV6C2832UBA
* [SHARP] LH28F16
* [TOSHIBA] TV00578002DABD
* [TOSHIBA] TV00578003DABD
* 2. [DA] Supports new NAND flash device.
* [TOSHIBA] TH58NVG1S8BFT
*
* Resolution for 156: [FlashTool v2.7.1013][BUG FIX] Fix BootROM start command failure while manually selecting NMT6226 or MT6227 baseband chip.
*
* Rev 1.11 Nov 24 2005 16:04:34 mtk00539
* 1. [DA][BUG FIX] Incorrectly detects S71PL127JXX as S71PL254JXX because da_memcmp() cannot work probably.
* Resolution for 149: [BROM_DLL v2.7.1011][New] Add UID Secure Booting feature and Bug Fix.
*
* Rev 1.10 Nov 19 2005 00:46:10 mtk00539
* 1. [BROM_DLL&DA][New] Add UID Secure Booting feature.
* 2. [BROM_DLL&DA][BUG FIX] Fix RTC date-time value could not be initialized problem.
* 3. [DA][New] Supports new NOR flash device.
* [INTEL] 38F1010C0ZBL0
* [INTEL] 28F1602C3BD70
* [TOSHIBA] TY0068B012APGG
* [TOSHIBA] TY0068B013APGG
* 4. [DA][New] Supports new NAND flash device.
* [HYNIX] HY27XG082G2M
* 5. [DA][BUF FIX] Refill BootLoader header for BootROM to identify NAND flash organization.
* Resolution for 149: [BROM_DLL v2.7.1011][New] Add UID Secure Booting feature and Bug Fix.
*
* Rev 1.9 Oct 19 2005 14:45:16 mtk00539
* 1. [BROM_DLL&DA][New] New H/W devices detection architecture including NOR, NAND, SRAM and DRAM detection.
* 2. [BROM_DLL&DA][New] DA partial download technic, that overcomes DA size exceeds MT6205B internal SRAM (32KB).
* 3. [BROM_DLL&DA][New] Format verification option, each byte should be 0xFF after erasure.
* 4. [BROM_DLL&DA][New] DA validation to ensure invalid binary could not be loaded.
* 5. [BROM_DLL&DA][New] Support NFB download.
* 6. [BROM_DLL&DA][New] Support NAND flash format with 3 method, NORMAL, FORCEDLY ERASE and MARK AS BAD BLOCK.
* 7. [BROM_DLL&DA][New] Support NAND flash read back with 4 methods, PAGE+ECC, PAGE ONLY, SPARE ONLY and PAGE+SPARE.
* Resolution for 140: [BROM_DLL v2.7.1008][New] Support NFB download and many new features.
*
* Rev 1.8 Oct 18 2005 13:37:10 mtk00539
* 1. [DA][New] New NOR flash device support
* [SILICON7] S7_SV7E160XT,
* [SILICON7] S7_SV7E160XB,
* [SILICON7] S7_SV7E320XT,
* [SILICON7] S7_SV7E320XB,
* [SPANSION] S71GL032R3_T,
* [SPANSION] S71GL032R4_B,
* [SPANSION] S71GL032R1R2,
* [TOSHIBA] TV00569002BABD,
* [TOSHIBA] TV00569003BABD,
* [TOSHIBA] TV00569002AABD,
* [TOSHIBA] TV00569003AABD,
* Resolution for 137: [BROM_DLL v2.4.1017][New] Enable SID feature and add new flash device supoprt.
*
* Rev 1.7 Feb 16 2005 17:24:26 mtk00539
* 1. [DA][BUG FIX] Fix INTEL W18/W30 series flash program fail. this series don't support Buffered-Program method, we can only use WORD program.
* 2. [DA][BUG FIX] Fix format %x bug in UART_Printf().
* 3. [DA][BUG FIX] Fix small size EXT_SRAM detection error. Shrink the EXT_SRAM detection unit from 512KB to 128KB in Board_Schematic().
* 4. [DA][New] Extend max sector region to 4 for SPANSION S71AL016D flash.
* 5. [DA][New] Add SPANSION S71AL016D T/B and SHARP LRS18C8A flash support.
* Resolution for 105: [BROM_DLL v2.4.1009][New] Fix INTEL W18/W30 series bug and add SPANSION S71AL016D and SHARP LRS18C8A flash support.
*
* Rev 1.6 Nov 22 2004 12:25:36 mtk00539
* 1. [DA][BUG FIX] Add data verification in status polling during erase or program operation.
* 2. [DA][BUG FIX] Fix two dies flash detection fail in INTEL_CheckDevID().
* 3. [DA][Change Behavior] When RX_BUFFER_FULL occurs, flush data queued in UART ring buffer til data is less than 512KB.
* 4. [DA][New] Support Buffered-Program method for INTEL family flashes.
* 5. [DA][New] Support new flashes [SHARP]LRS1828C and [RENESAS]M6MGB64BM34CDG.
* Resolution for 99: [BROM_DLL v2.4.1008][New] Support INTEL family flash Buffered-Program method.
*
* Rev 1.5 Nov 05 2004 10:36:46 mtk00539
* 1. [DA][BUG FIX] Fix format progress report error, percentage variable should not just use uint8.
* 2. [DA][BUG FIX] Fix command error for AMD protection routines.
* 3. [DA][Enhance] Fix UART_Printf compile warning in UART.C
* Resolution for 96: [BROM_DLL v2.4.1007][New] Implement S/W compatible mechanism for MT6218B_FN and MT6218B_GN.
*
* Rev 1.4 Oct 29 2004 11:46:46 mtk00539
* 1. [DA][BUG FIX] Read CFI boot sector flag to determine AM49DL3208GT and S71PL032J, since both flashes have the same id, but different layout.
* 2. [DA][BUG FIX] Fix INTEL and RENESAS status checking flow.
* 3. [DA][Enhance] Dump more logs in TEST_ExtSRAM().
* 4. [DA][New] Support new flashes
* [SAMSUNG] K5J6316CTM
* [TOSHIBA] TH50VPF5682CDSB
* [TOSHIBA] TH50VPF5683CDSB
* [ISSI] IS75V16F128GS32
* [RENESAS] M6MGT64BM34CDG
* [ST] M30L0T7000T0, M36L0T7050T0
* [ST] M30L0T7000B0, M36L0T7050B0
* [SHARP] LRS1862
* [SHARP] LRS1806A
* [AMD] AM49DL3208GT
* [SPANSION] S29PL032J, S71PL032J
* Resolution for 92: [BROM_DLL v2.4.1006][BUG FIX] Fix AM49DL3208GT & S71PL032J download fail problem and some enhancement.
*
* Rev 1.3 Aug 23 2004 19:57:48 mtk00539
* [DA][BUG FIX] Fix AM49DL3208G sector layout error.
* Resolution for 86: [BROM_DLL v2.4.1003] Fix AM49DL3208G sector layout error.
*
* Rev 1.2 Aug 09 2004 17:52:06 mtk00539
* [BUG FIX] Ignore high byte of manufacture id
*
* Rev 1.1 Aug 03 2004 10:33:06 mtk00539
* 1. [DA][BUG FIX] Invoke Board_Schematic()(old name is HW_Init()) before FUTL_CheckDevice(). Because FUTL_CheckDevice() must know the absolute address for each bank.
* 2. [DA][New] Add 12 new flash devices support
* [SAMSUNG]K5A3280YT,
* [TOSHIBA]TH50VPF6782AASB,
* [TOSHIBA]TH50VPF6783AASB,
* [TOSHIBA]TV00578002AABD,
* [TOSHIBA]TV00578003AABD,
* [Fujitsu]MB84VP24581HK,
* [INTEL]INTEL_28F640W30_B,
* [SPANSION]AM49PDL127BH,
* [SPANSION]AM49PDL129BH,
* [RENESAS]M6MGD13BW66CDG,
* [Winbond]W19B322TM,
* [Winbond]W19B323TM,
* 3. [DA][New] Readback check after WORD program is done, so that DA won't have to keep the chksum.
* 4. [DA][New] Auto-detect baseband chip type.
* 5. [DA][New] Auto-detect external SRAM size.
* 6. [DA][New] Merge MT6205B, MT6218B and MT6219 to an all-in-one DA.
* 7. [DA][New] Merge flash stress test module.
* 8. [DA][New] Modify makefile to build ARM or THUMB code.
* 9. [DA][New] Construct a customization kit for customers to add new flash or SOC checking algorithm by themselves.
* 10. [DA][Enhance] Split out AM29PDL128G function to improve the performance of general AMD callback functions.
* 11. [DA][Enhance] Enhance RX_BUFF_FULL behavior to prevent always retry two times.
* Resolution for 83: [BROM_DLL v2.4.1002] Merge all the DAs into all-in-one DA and fix many bugs and enhancement.
*
* Rev 1.0 Jul 19 2004 01:44:00 mtk00539
* Initial revision.
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*==============================================================================
*******************************************************************************/
#include <string.h>
#include "flash_drv_AMD.h"
#include "hw_config.h"
//------------------------------------------------------------------------------
// Callback Function Set
//------------------------------------------------------------------------------
const NOR_CMD_Callback_S AMD_CMD_CB_UNLOCK_BYPASS_PGM = {
AMD_CheckDevID,
AMD_CheckDevIdle,
AMD_Erase_CMD,
AMD_Erase_CheckDone_By_Polling,
AMD_PreProcess,
DUMMY_Program_PostProcess,
AMD_UnlockBypass_Enter_CMD,
AMD_UnlockBypass_Exit_CMD,
AMD_UnlockBypass_Program_CMD,
AMD_Program_CheckDone_By_Toggle,
NULL,
NULL
};
const NOR_CMD_Callback_S AMD_CMD_CB_MIRRORBIT_BUF_PGM = {
AMD_CheckDevID,
AMD_CheckDevIdle,
AMD_MirrorBit_Erase_CMD,
AMD_Erase_CheckDone_By_Polling,
AMD_MirrorBit_PreProcess,
DUMMY_Program_PostProcess,
DUMMY_Program_Enter,
DUMMY_Program_Exit,
AMD_Word_Program_CMD,
AMD_Program_CheckDone_By_Toggle,
AMD_MirrorBit_Buf_Program_CMD,
AMD_Program_CheckDone_By_Toggle
};
const NOR_CMD_Callback_S AMD_CMD_CB_WORD_PGM = {
AMD_CheckDevID,
AMD_CheckDevIdle,
AMD_Erase_CMD,
AMD_Erase_CheckDone_By_Polling,
AMD_PreProcess,
DUMMY_Program_PostProcess,
DUMMY_Program_Enter,
DUMMY_Program_Exit,
AMD_Word_Program_CMD,
AMD_Program_CheckDone_By_Toggle,
NULL,
NULL
};
//------------------------------------------------------------------------------
// Memory Sector Layout Set
//------------------------------------------------------------------------------
const NOR_Die_Layout_S AMD_32 = {
0x00400000,
{
{ 0x00000000, 64, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_64 = {
0x00800000,
{
{ 0x00000000, 128, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
// Top Boot
const NOR_Die_Layout_S AMD_T_16 = {
0x00200000,
{
{ 0x00000000, 31, 0x10000 }
,{ 0x001F0000, 1, 0x8000 }
,{ 0x001F8000, 2, 0x2000 }
,{ 0x001FC000, 1, 0x4000 }
}
};
const NOR_Die_Layout_S AMD_T_32 = {
0x00400000,
{
{ 0x00000000, 63, 0x10000 }
,{ 0x003F0000, 8, 0x2000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_T_64 = {
0x00800000,
{
{ 0x00000000, 127, 0x10000 }
,{ 0x007F0000, 8, 0x2000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_T_128 = {
0x01000000,
{
{ 0x00000000, 255, 0x10000 }
,{ 0x00FF0000, 8, 0x2000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_T_256 = {
0x02000000,
{
{ 0x00000000, 511, 0x10000 }
,{ 0x01FF0000, 8, 0x2000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
// Bottom Boot
const NOR_Die_Layout_S AMD_B_16 = {
0x00200000,
{
{ 0x00000000, 1, 0x4000 }
,{ 0x00004000, 2, 0x2000 }
,{ 0x00008000, 1, 0x8000 }
,{ 0x00010000, 31, 0x10000 }
}
};
const NOR_Die_Layout_S AMD_B_32 = {
0x00400000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 63, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_B_64 = {
0x00800000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 127, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_B_128 = {
0x01000000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 255, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_B_256 = {
0x02000000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 511, 0x10000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
// Top/Bottom Boot
const NOR_Die_Layout_S AMD_TB_32 = {
0x00400000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 62, 0x10000 }
,{ 0x003F0000, 8, 0x2000 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_TB_64 = {
0x00800000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 126, 0x10000 }
,{ 0x007F0000, 8, 0x2000 }
,{ 0, 0, 0 }
}
};
const NOR_Die_Layout_S AMD_TB_128 = {
0x01000000,
{
{ 0x00000000, 8, 0x2000 }
,{ 0x00010000, 254, 0x10000 }
,{ 0x00FF0000, 8, 0x2000 }
,{ 0, 0, 0 }
}
};
//------------------------------------------------------------------------------
// MirrorBit Memory Sector Layout Set
//------------------------------------------------------------------------------
// MirrorBit Bottom Boot
const NOR_Die_Layout_S AMD_MB_B_64 = {
0x00800000,
{
{ 0x00000000, 4, 0x10000 }
,{ 0x00040000, 31, 0x40000 }
,{ 0, 0, 0 }
,{ 0, 0, 0 }
}
};
// MirrorBit Top Boot
const NOR_Die_Layout_S AMD_MB_T_64 = {
0x00800000,
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