📄 hw_config.h
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/*******************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2004
*
*******************************************************************************/
/*******************************************************************************
*
* Filename:
* ---------
* hw_config.h
*
* Project:
* --------
* FlashTool Download Agent
*
* Description:
* ------------
* This Module defines the H/W configuration.
*
* Author:
* -------
* Amos Hsu
*
*==============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
* $Revision: 1.10 $
* $Modtime: Jan 13 2006 14:55:38 $
* $Log: //mtkvs01/vmdata/flash_tool/archives/DA/INC/hw_config.h-arc $
*
* Rev 1.10 Jan 14 2006 00:09:52 mtk00539
* Bug fixes:
* 1. [DA] Workaround reading DSP version failure issue in some production lines, rollback to the old method for reading DSP version.
*
* New features:
* 1. [DA] Supports INTEL Sibley family flash.
* 2. [DA] Supports new NOR flash device.
* [INTEL] PF38F5050M0XXXX
* Resolution for 159: [FlashTool v2.7.1015]
*
* Rev 1.9 Nov 27 2005 16:38:00 mtk00539
* 1. [DA][BUG FIX] Use mem_overlap_copy() instead of memcpy() to fix RegionRelocation() failure.
* Resolution for 151: [BROM_DLL v2.7.1012][BUG FIX] Cannot recognize 05B ROM_INFO header.
*
* Rev 1.8 Nov 24 2005 16:04:44 mtk00539
* 1. [DA][BUG FIX] Incorrectly detects S71PL127JXX as S71PL254JXX because da_memcmp() cannot work probably.
* Resolution for 149: [BROM_DLL v2.7.1011][New] Add UID Secure Booting feature and Bug Fix.
*
* Rev 1.7 Nov 19 2005 00:43:22 mtk00539
* 1. [BROM_DLL&DA][New] Add UID Secure Booting feature.
* 2. [BROM_DLL&DA][BUG FIX] Fix RTC date-time value could not be initialized problem.
* 3. [DA][New] Supports new NOR flash device.
* [INTEL] 38F1010C0ZBL0
* [INTEL] 28F1602C3BD70
* [TOSHIBA] TY0068B012APGG
* [TOSHIBA] TY0068B013APGG
* 4. [DA][New] Supports new NAND flash device.
* [HYNIX] HY27XG082G2M
* Resolution for 149: [BROM_DLL v2.7.1011][New] Add UID Secure Booting feature and Bug Fix.
*
* Rev 1.6 Oct 19 2005 14:45:02 mtk00539
* 1. [BROM_DLL&DA][New] New H/W devices detection architecture including NOR, NAND, SRAM and DRAM detection.
* 2. [BROM_DLL&DA][New] DA partial download technic, that overcomes DA size exceeds MT6205B internal SRAM (32KB).
* 3. [BROM_DLL&DA][New] Format verification option, each byte should be 0xFF after erasure.
* 4. [BROM_DLL&DA][New] DA validation to ensure invalid binary could not be loaded.
* 5. [BROM_DLL&DA][New] Support NFB download.
* 6. [BROM_DLL&DA][New] Support NAND flash format with 3 method, NORMAL, FORCEDLY ERASE and MARK AS BAD BLOCK.
* 7. [BROM_DLL&DA][New] Support NAND flash read back with 4 methods, PAGE+ECC, PAGE ONLY, SPARE ONLY and PAGE+SPARE.
* Resolution for 140: [BROM_DLL v2.7.1008][New] Support NFB download and many new features.
*
* Rev 1.5 May 24 2005 19:56:08 mtk00539
* 1. [DA][New] Support new flash devices S71PL254JXX, S71WS256NXX.
* 2. [DA][New] Add DA_ENABLE_WATCHDOG_CMD command to enable watchdog.
* Resolution for 115: [BROM_DLL v2.4.1012][New] Support new flash devices and bug fix.
*
* Rev 1.4 Mar 29 2005 11:14:38 mtk00539
* 1. [BROM_DLL][BUG FIX] ROM_ID_Class::LoadID() should dump only the last 256 bytes data.
* 2. [BROM_DLL][New] Add detail H/W error debug log.
* 3. [DA][Enhance] Enhance bus test in FlashTest_DA.
* 4. [DA][New] Add H/W error detail detection, thus we can distinguish INT_SRAM or EXT_SRAM error.
* 5. [DA][New] Add all INTEL W18/W30, L18/L30 non-SCSP flashes support.
* Resolution for 107: [BROM_DLL v2.4.1010][New] Enhance bus test in FlashTest_DA, new INTEL flash support and bug fix.
*
* Rev 1.3 Sep 17 2004 17:02:00 mtk00539
* [DA][Enhance] Return error when DA can not detect internal and external SRAM size correctly.
* Resolution for 90: [BROM_DLL v2.4.1005][BUG FIX] Fix MT6217 download fail problem and some enhancement.
*
* Rev 1.2 Sep 14 2004 20:50:18 mtk00539
* 1. [DA][BUG FIX] Fix MT6217 download fail problem by implement internal SRAM auto-detection mechanism.
* Resolution for 90: [BROM_DLL v2.4.1005][BUG FIX] Fix MT6217 download fail problem and some enhancement.
*
* Rev 1.1 Aug 03 2004 10:42:44 mtk00539
* 1. [DA][BUG FIX] Invoke Board_Schematic()(old name is HW_Init()) before FUTL_CheckDevice(). Because FUTL_CheckDevice() must know the absolute address for each bank.
* 2. [DA][New] Add 12 new flash devices support
* [SAMSUNG]K5A3280YT,
* [TOSHIBA]TH50VPF6782AASB,
* [TOSHIBA]TH50VPF6783AASB,
* [TOSHIBA]TV00578002AABD,
* [TOSHIBA]TV00578003AABD,
* [Fujitsu]MB84VP24581HK,
* [INTEL]INTEL_28F640W30_B,
* [SPANSION]AM49PDL127BH,
* [SPANSION]AM49PDL129BH,
* [RENESAS]M6MGD13BW66CDG,
* [Winbond]W19B322TM,
* [Winbond]W19B323TM,
* 3. [DA][New] Readback check after WORD program is done, so that DA won't have to keep the chksum.
* 4. [DA][New] Auto-detect baseband chip type.
* 5. [DA][New] Auto-detect external SRAM size.
* 6. [DA][New] Merge MT6205B, MT6218B and MT6219 to an all-in-one DA.
* 7. [DA][New] Merge flash stress test module.
* 8. [DA][New] Modify makefile to build ARM or THUMB code.
* 9. [DA][New] Construct a customization kit for customers to add new flash or SOC checking algorithm by themselves.
* 10. [DA][Enhance] Split out AM29PDL128G function to improve the performance of general AMD callback functions.
* 11. [DA][Enhance] Enhance RX_BUFF_FULL behavior to prevent always retry two times.
* Resolution for 83: [BROM_DLL v2.4.1002] Merge all the DAs into all-in-one DA and fix many bugs and enhancement.
*
* Rev 1.0 Jul 19 2004 01:47:10 mtk00539
* Initial revision.
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*==============================================================================
*******************************************************************************/
#ifndef _HW_CONFIG_H_
#define _HW_CONFIG_H_
#include "SW_TYPES.H"
#include "DOWNLOAD.H"
#include "mtk_mcu.h"
extern uint32 Image$$MAIN_PROG$$Limit;
extern uint32 Image$$MAIN_PROG$$ZI$$Limit;
extern uint32 Image$$NAND_MODULE$$ZI$$Limit;
#define DA_MAIN_PROG_END_ADDR ((uint32)&Image$$MAIN_PROG$$Limit)
#define DA_MAIN_PROG_ZI_END_ADDR ((uint32)&Image$$MAIN_PROG$$ZI$$Limit)
#define DA_NAND_MODULE_END_ADDR ((uint32)&Image$$NAND_MODULE$$ZI$$Limit)
#define INT_SRAM_BASEADDR 0x40000000
#define RAMSIZE_BEGIN_PATTERN "<<<RAM_BEGIN>>>"
#define RAMSIZE_END_PATTERN "<<<RAM_END>>>"
typedef struct {
BBCHIP_TYPE m_bbchip_type;
uint32 m_hw_code;
uint32 m_hw_ver;
} HW_BB_CHIP_ID_S;
typedef struct {
uint32 m_baseaddr;
volatile uint32 *m_reg_emi_con;
} HW_BB_EMI_Bank_S;
typedef struct {
HW_BB_EMI_Bank_S m_bank[MAX_CS];
bool m_is_mobile_ram_support;
volatile uint32 *m_reg_emi_gen_a;
volatile uint32 *m_reg_emi_gen_b;
volatile uint32 *m_reg_emi_con_i;
volatile uint32 *m_reg_emi_con_j;
volatile uint32 *m_reg_emi_con_k;
volatile uint32 *m_reg_emi_con_l;
} HW_BB_EMI_Config_S;
typedef struct {
volatile uint16 *m_reg_highspeed_uart;
volatile uint16 *m_reg_sample_count;
volatile uint16 *m_reg_sample_point;
} HW_BB_UART_Config_S;
typedef struct {
uint32 m_dummy;
} HW_BB_DMA_Config_S;
typedef struct {
uint32 m_dummy;
} HW_BB_INT_Config_S;
typedef struct {
uint16 m_timeout_shift_bits;
} HW_BB_RGU_Config_S;
typedef struct {
volatile uint16 *m_reg_gpio_mod_ctrl_4;
uint32 m_nfi_mask;
uint32 m_nfi_cs0;
uint32 m_nfi_cs1;
} HW_BB_GPIO_Config_S;
typedef struct {
volatile uint16 *m_reg_power_down_clear_0;
volatile uint16 *m_reg_power_down_clear_1;
} HW_BB_PDN_Config_S;
typedef struct {
bool m_nfi_v2;
} HW_BB_NFI_Config_S;
struct _HW_Device_Config_S;
typedef struct _HW_Device_Config_S HW_Device_Config_S;
typedef bool (*CB_SETUP_PLL)(HW_Device_Config_S *p_hw_dev_cfg);
typedef struct {
volatile uint16 *m_reg_mdpll;
volatile uint16 *m_reg_clk_con;
volatile uint16 *m_reg_mcuclk_con;
CB_SETUP_PLL m_cb_setup_pll;
} HW_BB_CLK_Config_S;
typedef struct {
const HW_BB_CHIP_ID_S m_ID;
const HW_BB_EMI_Config_S *m_EMI;
const HW_BB_UART_Config_S *m_UART;
const HW_BB_DMA_Config_S *m_DMA;
const HW_BB_INT_Config_S *m_INT;
const HW_BB_RGU_Config_S *m_RGU;
const HW_BB_GPIO_Config_S *m_GPIO;
const HW_BB_PDN_Config_S *m_PDN;
const HW_BB_NFI_Config_S *m_NFI;
const HW_BB_CLK_Config_S *m_CLK;
const bool m_SB_Support;
} HW_BB_Config_S;
typedef struct {
// storage type
HW_StorageType_E m_type;
// flash chip-select
HW_ChipSelect_E m_chip_select[MAX_DIE_IN_MCP];
// NOR flash base address
uint32 m_nor_baseaddr[MAX_DIE_IN_MCP];
// NOR flash setting
uint32 m_nor_emi_con;
// NAND flash setting
uint32 m_nand_acccon;
} HW_Storage_Config_S;
typedef struct {
// external ram type
HW_RAMType_E m_type;
// external ram chip-select
HW_ChipSelect_E m_chip_select;
// external ram base address
uint32 m_baseaddr;
// external ram size
uint32 m_size;
// external sram setting
uint32 m_sram_emi_con;
// external mobile ram setting
uint32 m_emi_gen_a;
uint32 m_emi_gen_b;
uint32 m_emi_dram_con_i_mode;
uint32 m_emi_dram_con_i_ext_mode;
// uint32 m_emi_dram_con_j;
uint32 m_emi_dram_con_k;
uint32 m_emi_dram_con_l;
// internal sram size
uint32 m_int_sram_size;
} HW_RAM_Config_S;
typedef struct {
// external clock
EXT_CLOCK m_ext_clock;
} HW_CLK_Config_S;
struct _HW_Device_Config_S {
// storage config
HW_Storage_Config_S m_storage_cfg;
// ram config
HW_RAM_Config_S m_ram_cfg;
// clock config
HW_CLK_Config_S m_clk_cfg;
// baseband config
const HW_BB_Config_S *m_hw_bbcfg;
};
typedef struct {
// bbchip
BBCHIP_TYPE m_bbchip;
uint16 m_bbchip_hw_code;
uint16 m_bbchip_hw_ver;
uint16 m_bbchip_sw_ver;
// storagte report
STATUS_E m_storage_ret;
HW_StorageType_E m_storage_type;
HW_ChipSelect_E m_storage_chip_select[2];
uint16 m_flash_id;
uint32 m_flash_size;
uint16 m_flash_dev_code_1;
uint16 m_flash_dev_code_2;
uint16 m_flash_dev_code_3;
uint16 m_flash_dev_code_4;
// only valid for NAND flash
uint16 m_nand_pagesize;
uint16 m_nand_sparesize;
uint16 m_nand_pages_per_block;
uint8 m_nand_io_interface;
uint8 m_nand_addr_cycle;
// internal sram report
STATUS_E m_int_sram_ret;
uint32 m_int_sram_size;
// external ram report
STATUS_E m_ext_ram_ret;
HW_RAMType_E m_ext_ram_type;
HW_ChipSelect_E m_ext_ram_chip_select;
uint32 m_ext_ram_size;
} HW_DetectionResult_S;
#ifdef __cplusplus
extern "C" {
#endif
extern HW_Device_Config_S g_HW_DevCfg;
extern HW_DetectionResult_S g_HW_DetectionResult;
#define EMI_BANK_BASEADDR(p_hw_bbcfg, ecs) ((CS_WITH_DECODER==ecs)?CS_WITH_DECODER:p_hw_bbcfg->m_EMI->m_bank[ecs].m_baseaddr)
#define EMI_BANK_REG(p_hw_bbcfg, ecs) (p_hw_bbcfg->m_EMI->m_bank[ecs].m_reg_emi_con)
extern int32 mem_overlap_copy(void *dest, void *src, uint32 len);
extern BBCHIP_TYPE DetectBasebandChip(void);
extern STATUS_E SetupEMI_DRAM(HW_ChipSelect_E cs);
extern STATUS_E SetupEMI(HW_ChipSelect_E cs, uint32 emi_setting);
extern STATUS_E DetectIntSRAM(uint32 *p_size);
extern STATUS_E DetectExtRAM(HW_RAMType_E *p_type, HW_ChipSelect_E *p_chip_select, uint32 *p_baseaddr, uint32 *p_size);
extern void SchematicSetup(HW_DetectionResult_S *p_result);
#ifdef __cplusplus
}
#endif
#endif
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