加法器树乘法器.txt

加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity ywxj_multipier is 
port(clk: in std_logic; 
a: in std_logic_vector(7 downto 0);--乘数 
b: in std_logic_vector(7 downto 0);--被乘数 
y: out std_logic_vector(15 downto 0));--输出 
end ywxj_multipier; 
architecture rtl of ywxj_multipier is 

begin 
p1: process(clk) 
variable n0,n1,n2,n3,n4,n5,n6,n7: std_logic_vector(15 downto 0); 
variable m: std_logic_vector(7 downto 0); 

begin 
m:="00000000"; 
if clk'event and clk='1' then 
if a(0)<='0' then 
n0:="0000000000000000"; 
else 
n0:=m&b; 
end if; 

if a(1)<='0' then 
n1:="0000000000000000"; 
else 
n1:=m(7 downto 1)&b&m(0); 
end if; 

if a(2)<='0' then 
n2:="0000000000000000"; 
else 
n2:=m(7 downto 2)&b&m(1 downto 0); 
end if; 

if a(3)<='0' then 
n3:="0000000000000000"; 
else 
n3:=m(7 downto 3)&b&m(2 downto 0); 
end if; 

if a(4)<='0' then 
n4:="0000000000000000"; 
else 
n4:=m(7 downto 4)&b&m(3 downto 0); 
end if; 

if a(5)<='0' then 
n5:="0000000000000000"; 
else 
n5:=m(7 downto 5)&b&m(4 downto 0); 
end if; 

if a(6)<='0' then 
n6:="0000000000000000"; 
else 
n6:=m(7 downto 6)&b&m(5 downto 0); 
end if; 

if a(7)<='0' then 
n7:="0000000000000000"; 
else 
n7:=m(7)&b&m(6 downto 0); 
end if; 
y<=n0+n1+n2+n3+n4+n5+n6+n7; 
end if; 
end process p1; 
end rtl;