📄 dsp builder.mht
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Overview</STRONG></EM></P>
<P><A=20
=
href=3D"http://www.altera.com/products/software/products/dsp/images/dsp-b=
uilder_fig1.pdf"><IMG=20
height=3D253 alt=3D"Figure 1: DSP Builder Overview"=20
=
src=3D"http://www.altera.com/products/software/products/dsp/images/dsp-bu=
ilder_fig1.gif"=20
width=3D400 border=3D0><BR><IMG height=3D16=20
alt=3D"Click for full detail (652 KB)"=20
=
src=3D"http://www.altera.com/products/ip/images/ipms_pdf.gif"=20
width=3D16 border=3D0> Click for full detail (652 =
KB)</A></P>
<P>Altera MegaCore functions are high-level, =
parameterized=20
intellectual property (IP) functions such as =
finitie=20
impulse Response (FIR) filters and fast fourier=20
transforms (FFT) that can be configured to meet system =
performance requirements fast and easily. MegaCore =
functions=20
support Altera's IP evaluation features, =
which=20
allow customers to verify the functionality and timing =
of a=20
function prior to purchasing a license.</P>
<UL>
<LI>The OpenCore<SUP>=C2=AE</SUP> evaluation =
feature lets=20
designers test-drive IP cores without =
cost using=20
the Quartus II software; however, designers =
cannot=20
generate device programming files to test the core =
in=20
hardware.=20
<LI>The OpenCore Plus evaluation feature enhances =
the=20
OpenCore evaluation feature by supporting free =
hardware=20
evaluation. This feature allows you to generation=20
of time-limited programming files for a design =
that=20
includes Altera MegaCore functions. With these =
files,=20
designers can perform board-level design =
verification before=20
deciding to purchase licenses for the MegaCore =
functions.=20
</LI></UL>
<P>With both evaluation features, a license should be=20
purchased when the customer is completely =
satisfied with=20
a core's functionality and performance, and would like =
to take=20
their design to production.</P>
<P>The DSP Builder SignalCompiler block reads Simulink =
Model=20
Files (<STRONG>.mdl</STRONG>) that are built using DSP =
Builder=20
and MegaCore blocks and generates VHDL files and Tcl =
scripts=20
for synthesis, hardware implementation, and =
simulation.=20
Figure 2 shows the DSP builder design flow.</P>
<P><EM><STRONG>Figure 2: DSP Builder Design=20
Flow</STRONG></EM></P>
<P><A=20
=
href=3D"http://www.altera.com/products/software/products/dsp/images/dsp-b=
uilder_fig2.pdf"><IMG=20
height=3D275 alt=3D"Figure 2: DSP Builder Design Flow" =
=
src=3D"http://www.altera.com/products/software/products/dsp/images/dsp-bu=
ilder_fig2.gif"=20
width=3D228 border=3D0><BR><BR><IMG height=3D16=20
alt=3D"Click for full detail (652 KB)"=20
=
src=3D"http://www.altera.com/products/ip/images/ipms_pdf.gif"=20
width=3D16 border=3D0> Click for full detail (23 =
KB)</A></P>
<H3>Related Links</H3>
<UL>
<LI><A=20
=
href=3D"http://www.altera.com/products/ip/dsp/transforms/m-ham-fft.html">=
FFT=20
MegaCore Function</A>=20
<LI><A=20
=
href=3D"http://www.altera.com/products/ip/dsp/filtering/m-alt-fir-compile=
r.html">FIR=20
Compiler MegaCore Function</A>=20
<LI><A=20
=
href=3D"http://www.altera.com/products/ip/dsp/signal_generation/m-alt-nco=
compiler.html">NCO=20
Compiler</A>=20
<LI><A=20
=
href=3D"http://www.altera.com/products/ip/dsp/error_detection_correction/=
m-alt-rs-compiler.html">Reed-Solomon=20
Compiler MegaCore Function</A>=20
<LI><A=20
=
href=3D"http://www.altera.com/products/ip/dsp/error_detection_correction/=
m-alt-viterbi-compiler.html">Viterbi=20
Compiler MegaCore Function</A>=20
<LI><A=20
=
href=3D"http://www.mathworks.com/products/connections/trials/altera.shtml=
">The=20
MathWorks: MATLAB & Simulink Product Evaluation =
for Use=20
with Altera DSP Builder</A>=20
<LI><A=20
=
href=3D"https://buy.altera.com/etraining/start.swe?SWEMethod=3DDrilldown&=
amp;SWEApplet=3DeTraining+Course+List+Applet&SWEView=3DeTraining+Cour=
se+List+View&SWEApcnt=3D1&SWEField=3Dl_Name&SWECmd=3DInvokeMe=
thod&SWECount=3D1&SWERowIds=3DSWERowId0=3D1-11VNEV">Altera=20
class: DSP Design Series Part I: Implementing DSP =
Designs in=20
FPGAs</A>=20
<LI><A=20
=
href=3D"https://buy.altera.com/etraining/start.swe?SWEMethod=3DDrilldown&=
amp;SWEApplet=3DeTraining+Course+List+Applet&SWEView=3DeTraining+Cour=
se+List+View&SWEApcnt=3D1&SWEField=3Dl_Name&SWECmd=3DInvokeMe=
thod&SWECount=3D1&SWERowIds=3DSWERowId0=3D1-11VNEZ">Altera=20
class: DSP Design Series Part II: Using FPGAs to =
Architect=20
and Optimize a DSP System</A> =
</LI></UL><!--stopindex--><!-- end content =
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