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<H2>DSP Builder</H2>
<P>The DSP Builder is a digital signal processing =
(DSP)=20
development tool that interfaces between the=20
Quartus<SUP>=C2=AE</SUP> II software and =
MATLAB/Simulink=20
tools.</P>
<UL>
<LI><A=20
=
href=3D"http://www.altera.com/literature/ug/ug_dsp_builder.pdf"><EM>DSP=20
Builder User Guide</EM></A>=20
<LI><A=20
=
href=3D"http://www.altera.com/literature/manual/mnl_dsp_builder.pdf"><EM>=
DSP=20
Builder Reference Manual</EM></A>=20
<LI><A=20
=
href=3D"http://www.altera.com/products/software/products/dsp/dsp_builder_=
lic.html?function=3Ddsp_builder">Download=20
the DSP Builder</A> </LI></UL>
<H3>New in Version 2.2.0</H3>
<UL>
<LI>Support for Stratix<SUP>=C2=AE</SUP> II and =
Cyclone=E2=84=A2 II=20
devices=20
<LI>Support for the Quartus II software, =
version 4.1=20
and higher=20
<LI>Support for MATLAB version 7.0 and Simulink =
version 6.0=20
<LI>Verilog HDL simulation support=20
<LI>New blocks:=20
<UL>
<LI>VCD Sink block (AltLab library)=20
<LI>Sum of Products block (Arithmetic library)=20
<LI>1-to-n Demultiplexer block (Gate library)=20
<LI>
<DIV>Square Root block (Arithmetic library) </DIV>
<LI>
<DIV>Bus Probe block (AltLab library) =
</DIV></LI></UL>
<LI>Added support for use of=20
MegaCore<SUP>=C2=AE</SUP> functions=20
<LI>Support for multiple non-PLL clock domains =
</LI></UL>
<H3>Features</H3>
<UL>
<LI>Links The Mathworks MATLAB (Signal Processing =
ToolBox=20
and Filter Design Toolbox) and Simulink software =
with the=20
Altera<SUP>=C2=AE</SUP> Quartus II software=20
<LI>Supports the following Altera device families:=20
<UL>
<LI>Stratix, Stratix II, and Stratix GX devices=20
<LI>Cyclone and Cyclone II devices=20
<LI>APEX=E2=84=A2 II, APEX 20KC, and APEX 20KE =
devices=20
<LI>Mercury=E2=84=A2 devices=20
<LI>ACEX<SUP>=C2=AE</SUP> 1K devices=20
<LI>FLEX<SUP>=C2=AE</SUP> 10K and FLEX 6000 =
devices=20
</LI></UL>
<LI>Enables rapid prototyping using Altera DSP =
development=20
boards=20
<LI>Supports the SignalTap<SUP>=C2=AE</SUP> II =
logic=20
analyzer, an embedded signal analyzer that probes =
signals=20
from the Altera device on the DSP board and imports =
the data=20
into the MATLAB work space to facilitate visual =
analysis=20
<LI>Includes blocks that you can use to build custom =
logic=20
that works with Nios<SUP>=C2=AE</SUP> II and =
other SOPC=20
Builder designs=20
<LI>Includes a PLL block for multi-clock designs=20
<LI>Includes a state machine block=20
<LI>Supports a unified representation of the =
algorithm and=20
implementation of a DSP system=20
<LI>Automatically generates a VHDL testbench or =
Quartus II=20
Vector File (.<STRONG>vec</STRONG>) from MATLAB and =
Simulink=20
test vectors=20
<LI>Automatically starts Quartus II compilation=20
<LI>Enables bit- and cycle-accurate design =
simulation=20
<LI>Provides a variety of fixed-point arithmetic and =
logical=20
operators for use with the Simulink software =
</LI></UL>
<H3>General Description</H3>
<P><IMG height=3D139 alt=3D"DSP Builder" hspace=3D10=20
=
src=3D"http://www.altera.com/products/software/products/dsp/images/m-alt-=
dspbuilder_graphic_small.jpg"=20
width=3D108 align=3Dleft border=3D0>DSP system design =
in Altera=20
programmable logic devices (PLDs) requires both =
high-level=20
algorithm and hardware description language (HDL) =
development=20
tools. The Altera DSP Builder integrates these tools =
by=20
combining the algorithm development, simulation, and=20
verification capabilities of The MathWorks MATLAB and =
Simulink=20
system-level design tools with VHDL synthesis, =
simulation, and=20
Altera development tools. The DSP Builder shortens DSP =
design=20
cycles by helping designers create the hardware =
representation=20
of a DSP design in an algorithm-friendly development=20
environment. The existing MATLAB functions and =
Simulink blocks=20
can be combined with Altera DSP Builder blocks and =
Altera=20
intellectual property (IP) =
MegaCore functions to=20
link system-level design and implementation with DSP =
algorithm=20
development. DSP Builder allows system, algorithm, and =
hardware designers to share a common development =
platform.</P>
<P>Designers can use the blocks in DSP Builder to =
create a=20
hardware implementation of a system modeled in =
Simulink in=20
sampled time. DSP Builder contains bit- and =
cycle-accurate=20
Simulink blocks, which cover basic operations such as=20
arithmetic or storage functions. Complex functions can =
be=20
integrated by using MegaCore functions in DSP Builder =
models.=20
See Figure 1.</P>
<P><EM><STRONG>Figure 1. DSP Builder=20
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