sysinfo2.h

mstar 776 开发的车载dvd

//------------------------------------------------------------------------------
// ODCLK clock setting
//------------------------------------------------------------------------------
/*#define ODCLK_CLOCK_ADC             0x00
#define ODCLK_CLOCK_DVI             0x01
#define ODCLK_CLOCK_VD              0x02
#define ODCLK_CLOCK_MPEG0           0x03
#define ODCLK_CLOCK_1               0x04
#define ODCLK_CLOCK_EX_DI           0x05
#define ODCLK_CLOCK_XTAL_0          0x06
#define ODCLK_CLOCK_LPLL            0x07
#define ODCLK_CLOCK_XTAL_1          0x08

#define ODCLK_CLOCK_ENABLE          TRUE
#define ODCLK_CLOCK_INVERT          TRUE
#define ODCLK_CLOCK_SEL             ODCLK_CLOCK_ADC*/

#define ODCLK_CLOCK_ADC             0x00
#define ODCLK_CLOCK_VD              0x01
#define ODCLK_CLOCK_1               0x02
#define ODCLK_CLOCK_EX_DI           0x03
#define ODCLK_CLOCK_XTAL_0          0x04
#define ODCLK_CLOCK_LPLL            0x05
#define ODCLK_CLOCK_XTAL_1          0x06

#define ODCLK_CLOCK_ENABLE          TRUE
#define ODCLK_CLOCK_INVERT          FALSE
#define ODCLK_CLOCK_SEL             ODCLK_CLOCK_LPLL


/*
//------------------------------------------------------------------------------
// VEIN clock setting
//------------------------------------------------------------------------------
#define VEIN_CLOCK_ADC              0x00
#define VEIN_CLOCK_DVI              0x01
#define VEIN_CLOCK_VD               0x02
#define VEIN_CLOCK_MPEG0            0x03
#define VEIN_CLOCK_1                0x04
#define VEIN_CLOCK_EX_DI            0x05
#define VEIN_CLOCK_XTAL_0           0x06
#define VEIN_CLOCK_LPLL             0x07
#define VEIN_CLOCK_XTAL_1           0x08

#define VEIN_CLOCK_ENABLE           TRUE
#define VEIN_CLOCK_INVERT           FALSE
#define VEIN_CLOCK_SEL              VEIN_CLOCK_MPEG0

//------------------------------------------------------------------------------
// FCIE clock setting
//------------------------------------------------------------------------------
#define FCIE_CLOCK_86D256           0x00
#define FCIE_CLOCK_86D64            0x01
#define FCIE_CLOCK_86D16            0x02
#define FCIE_CLOCK_54D4             0x03
#define FCIE_CLOCK_72D4             0x04
#define FCIE_CLOCK_86D4             0x05
#define FCIE_CLOCK_54D2             0x06
#define FCIE_CLOCK_72D2             0x07
#define FCIE_CLOCK_86D2             0x08
#define FCIE_CLOCK_54MHZ            0x09
#define FCIE_CLOCK_72MHZ            0x0A
#define FCIE_CLOCK_0_0              0x0B
#define FCIE_CLOCK_0_1              0x0C
#define FCIE_CLOCK_0_2              0x0D
#define FCIE_CLOCK_0_3              0x0E
#define FCIE_CLOCK_0_4              0x0F
#define FCIE_CLOCK_XTAL             0x10

#define FCIE_CLOCK_ENABLE           FALSE
#define FCIE_CLOCK_INVERT           FALSE
#define FCIE_CLOCK_SEL              FCIE_CLOCK_86D256

//------------------------------------------------------------------------------
// TS clock setting
//------------------------------------------------------------------------------
#define TS2_CLOCK_TS2               0x00
#define TS2_CLOCK_0_0               0x01
#define TS2_CLOCK_0_1               0x02
#define TS2_CLOCK_XTAL              0x03

#define TS2_CLOCK_ENABLE            FALSE
#define TS2_CLOCK_INVERT            FALSE
#define TS2_CLOCK_SEL               TS2_CLOCK_TS2

//------------------------------------------------------------------------------
// TSOUT clock setting
//------------------------------------------------------------------------------
#define TSOUT_CLOCK_27MHZ           0x00
#define TSOUT_CLOCK_36MHZ           0x01
#define TSOUT_CLOCK_43MHZ           0x02
#define TSOUT_CLOCK_XTAL            0x03

#define TSOUT_CLOCK_ENABLE          FALSE
#define TSOUT_CLOCK_INVERT          FALSE
#define TSOUT_CLOCK_SEL             TSOUT_CLOCK_27MHZ
*/


//------------------------------------------------------------------------------
// IDCLK1 clock setting
//------------------------------------------------------------------------------
#define IDCLK1_CLOCK_ADC            0x00
#define IDCLK1_CLOCK_VD             0x01
#define IDCLK1_CLOCK_DC0            0x02
#define IDCLK1_CLOCK_VD20           0x03
#define IDCLK1_CLOCK_EX_DI          0x04
#define IDCLK1_CLOCK_VDADC          0x05
#define IDCLK1_CLOCK_0              0x06
#define IDCLK1_CLOCK_XTAL           0x07

#define IDCLK1_CLOCK_ENABLE         TRUE
#define IDCLK1_CLOCK_INVERT         FALSE
#define IDCLK1_CLOCK_SEL            IDCLK1_CLOCK_XTAL

//------------------------------------------------------------------------------
// IDCLK2 clock setting
//------------------------------------------------------------------------------
/*#define IDCLK2_CLOCK_ADC            0x00
#define IDCLK2_CLOCK_DVI            0x01
#define IDCLK2_CLOCK_VD             0x02
#define IDCLK2_CLOCK_DC0            0x03
#define IDCLK2_CLOCK_1              0x04
#define IDCLK2_CLOCK_EX_DI          0x05
#define IDCLK2_CLOCK_VDADC          0x06
#define IDCLK2_CLOCK_0              0x07
#define IDCLK2_CLOCK_XTAL           0x08

#define IDCLK2_CLOCK_ENABLE         TRUE
#define IDCLK2_CLOCK_INVERT         FALSE
#define IDCLK2_CLOCK_SEL            IDCLK2_CLOCK_XTAL*/

#define IDCLK2_CLOCK_ADC            0x00
#define IDCLK2_CLOCK_VD             0x01
#define IDCLK2_CLOCK_DC0            0x02
#define IDCLK2_CLOCK_VD20           0x03
#define IDCLK2_CLOCK_EX_DI          0x04
#define IDCLK2_CLOCK_VDADC          0x05
#define IDCLK2_CLOCK_0              0x06
#define IDCLK2_CLOCK_XTAL           0x07

#define IDCLK2_CLOCK_ENABLE         TRUE
#define IDCLK2_CLOCK_INVERT         FALSE
#define IDCLK2_CLOCK_SEL            IDCLK2_CLOCK_XTAL


/*
//------------------------------------------------------------------------------
// STRLD clock setting
//------------------------------------------------------------------------------
#define STRLD_CLOCK_144MHZ          0x00
#define STRLD_CLOCK_123MHZ          0x01
#define STRLD_CLOCK_108MHZ          0x02
#define STRLD_CLOCK_XTAL            0x03

#define STRLD_CLOCK_ENABLE          TRUE
#define STRLD_CLOCK_INVERT          FALSE
#define STRLD_CLOCK_SEL             STRLD_CLOCK_108MHZ
*/

/*
//------------------------------------------------------------------------------
// DHCDDR clock setting
//------------------------------------------------------------------------------
#define DHCDDR_CLOCK_GATING         FALSE
#define DHCDDR_CLOCK_INVERT         FALSE

//------------------------------------------------------------------------------
// DHCSYNTH clock setting
//------------------------------------------------------------------------------
#define DHCSYNTH_CLOCK_D2           0x00
#define DHCSYNTH_CLOCK_D2P5         0x01
#define DHCSYNTH_CLOCK_D3           0x02
#define DHCSYNTH_CLOCK_D4           0x03

#define DHCSYNTH_CLOCK_GATING       FALSE
#define DHCSYNTH_CLOCK_INVERT       FALSE
#define DHCSYNTH_CLOCK_SEL          DHCSYNTH_CLOCK_D2

//------------------------------------------------------------------------------
// DHCMCU clock setting
//------------------------------------------------------------------------------
#define DHCMCU_CLOCK_43MHZ          0x00
#define DHCMCU_CLOCK_54MHZ          0x01
#define DHCMCU_CLOCK_62MHZ          0x02
#define DHCMCU_CLOCK_72MHZ          0x03
#define DHCMCU_CLOCK_86MHZ          0x04
#define DHCMCU_CLOCK_108MHZ         0x05
#define DHCMCU_CLOCK_RESERVED       0x06

#define DHCMCU_CLOCK_GATING         FALSE
#define DHCMCU_CLOCK_INVERT         FALSE
#define DHCMCU_CLOCK_SEL            DHCMCU_CLOCK_43MHZ

//------------------------------------------------------------------------------
// DHCLIVE clock setting
//------------------------------------------------------------------------------
#define DHCLIVE_CLOCK_GATING        FALSE
#define DHCLIVE_CLOCK_INVERT        FALSE
*/

//------------------------------------------------------------------------------
// External interrupt activation type (0: low-level  1: falling-edge)
//------------------------------------------------------------------------------
#define EXINTR0_EDGE_TRIGGERED      1
#define EXINTR1_EDGE_TRIGGERED      0

#define DDRAM                       0
#define SDRAM                       1
#define X32                         0
#define X16                         1

//------------------------------------------------------------------------------
// Memory (FLASH /SRAM /SDRAM) base and len
//------------------------------------------------------------------------------
#define MIU_FLASH_BASE              0x0
#define MIU_FLASH_LEN               ( 0x10000*SYSTEM_BANK_NUM )

#define MIU_SDRAM_BASE              0x0
#define MIU_SDRAM_LEN               0x2000000           // 32M

//------------------------------------------------------------------------------
// XDATA memory map
//------------------------------------------------------------------------------

//- SRAM for dynamic memory allocation -----------------------------------------

#define XDATASRAM_START_ADDR        0x4000UL            // SRAM start address
#define XDATASRAM_SIZE              0x800               // 2K

//--------------------------- 38K DRAM for xdata -------------------------------

#define XDATA_DRAM_START_ADDR       0x4800UL            // DRAM for xdata mapping start address
#define MEMALLOC_POOL_SIZE          0x1F60              // 7.84K

#define XDATASDRAM_START_ADDR       (0UL - XD_MAP_BASE_ADR)
#define XDATASDRAM_SIZE             0xA800              // 42K

#define XDATA_WIN1_START_ADDR       0xF000UL
#define XDATA_WIN1_SIZE             0x1000

//------------------ dynamic 4K window for share memory ------------------------
#define GENBUFFER_START_ADDR        XDATA_WIN1_START_ADDR
#define GENBUFFER_POOL_SIZE         XDATA_WIN1_SIZE     // 4K

/*
//------------------------- FAT MAP of 4K window -------------------------------
#define FAT_TEMP_DIR1_ADR           GENBUFFER_START_ADDR//[1]1TH 4K
#define FAT_TEMP_DIR1_LEN           0x200               // 512B
#define FAT_TEMP_DIR2_ADR           (FAT_TEMP_DIR1_ADR+FAT_TEMP_DIR1_LEN)
#define FAT_TEMP_DIR2_LEN           0x200               // 512B
#define FAT_PARENT_NAME1_ADR        (FAT_TEMP_DIR2_ADR+FAT_TEMP_DIR2_LEN)
#define FAT_PARENT_NAME1_LEN        0x100               // 256B
#define FAT_CHILD_NAME1_ADR         (FAT_PARENT_NAME1_ADR+FAT_PARENT_NAME1_LEN)
#define FAT_CHILD_NAME1_LEN         0x100               // 256B
#define FAT_PARENT_NAME2_ADR        (FAT_CHILD_NAME1_ADR+FAT_CHILD_NAME1_LEN)
#define FAT_PARENT_NAME2_LEN        0x100               // 256B
#define FAT_CHILD_NAME2_ADR         (FAT_PARENT_NAME2_ADR+FAT_PARENT_NAME2_LEN)
#define FAT_CHILD_NAME2_LEN         0x100               // 256B
#define FAT_DIRENTRY_CACHE_ADR      (FAT_CHILD_NAME2_ADR+FAT_CHILD_NAME2_LEN)
#define FAT_DIRENTRY_CACHE_LEN      0x400               // 1K
#define FAT_RWDATA_CACHE_ADR        (FAT_DIRENTRY_CACHE_ADR+FAT_DIRENTRY_CACHE_LEN)
#define FAT_RWDATA_CACHE_LEN        0x400               // 1K

#define FAT_TABLE_CACHE_ADR         GENBUFFER_START_ADDR//[2]2ED 4K
#define FAT_TABLE_CACHE_LEN         0x1000              // 4K

#define FAT_CLUSTER_CACHE_ADR       GENBUFFER_START_ADDR//[3]3RD 4K
#define FAT_CLUSTER_CACHE_LEN       0x200               // 512B
#define FAT_LONG_NAME_ADR           (FAT_CLUSTER_CACHE_ADR+FAT_CLUSTER_CACHE_LEN)
#define FAT_LONG_NAME_LEN           0x100               // 256B
#define FCTRL_FHANDLE_ADR           (FAT_LONG_NAME_ADR+FAT_LONG_NAME_LEN)
#define FCTRL_FHANDLE_LEN           0x200               // 512B
#define FCTRL_PATH_NAME1_ADR        (FCTRL_FHANDLE_ADR+FCTRL_FHANDLE_LEN)
#define FCTRL_PATH_NAME1_LEN        0x100               // 256B
#define FCTRL_PATH_NAME2_ADR        (FCTRL_PATH_NAME1_ADR+FCTRL_PATH_NAME1_LEN)
#define FCTRL_PATH_NAME2_LEN        0x100               // 256B

//------------------------------------------------------------------------------
*/

//------------------------------------------------------------------------------
// Calculate Scaler DNR Memory
//------------------------------------------------------------------------------

#include "panel.h"

// Memory alignment
#define MemAlignUnit                64UL   // 128bit alignment for buffer, 512bit for write limit
#define MemAlign(n, unit)           ((((n)+(unit)-1)/(unit))*(unit))

// Input Size
#define SDINPUT_WIDTH               720UL
#define SDINPUT_HEIGHT              576UL
#define HDINPUT_WIDTH               1920UL
#define HDINPUT_HEIGHT              1088UL
#define VGAINPUT_WIDTH              1680UL
#define VGAINPUT_HEIGHT             1050UL

#define LB_WIDTH                    _MIN(PANEL_WIDTH, SC_LINE_BUFFER_SIZE)

// DNR memory size for one buffer
#define HD_DNR_16BIT                MemAlign(_MIN(HDINPUT_WIDTH, LB_WIDTH) * HDINPUT_HEIGHT * 2, MemAlignUnit)
#define HD_DNR_16BIT_HALF_HIGHT     MemAlign(_MIN(HDINPUT_WIDTH, LB_WIDTH) * HDINPUT_HEIGHT / 2 * 2, MemAlignUnit)

#define VGA_DNR_24BIT               MemAlign(_MIN(VGAINPUT_WIDTH, LB_WIDTH) * _MIN(VGAINPUT_HEIGHT, PANEL_HEIGHT) * 3, MemAlignUnit)

#define VGA_DNR_24BIT_QUARTER       MemAlign(VGA_DNR_24BIT / 4, MemAlignUnit)
#define SD_DNR_8BIT                 MemAlign(_MIN(SDINPUT_WIDTH, LB_WIDTH) * SDINPUT_HEIGHT * 1, MemAlignUnit)
#define SD_DNR_16BIT                MemAlign(_MIN(SDINPUT_WIDTH, LB_WIDTH) * SDINPUT_HEIGHT * 2, MemAlignUnit)
#define SD_DNR_24BIT                MemAlign(_MIN(SDINPUT_WIDTH, LB_WIDTH) * SDINPUT_HEIGHT * 3, MemAlignUnit)

//#define SCALER_MEM_SIZE             (_MAX(_MAX(HD_DNR_16BIT, VGA_DNR_24BIT), _MAX(SD_DNR_24BIT, SD_DNR_24BIT)) * 2)
#define SCALER_MEM_SIZE             (_MAX(_MAX(HD_DNR_16BIT, HD_DNR_16BIT), _MAX(SD_DNR_24BIT, SD_DNR_24BIT)) * 2)