drv2005.h

mstar 776 开发的车载dvd

/**********************************************************************
 * DRV2005.H
 * Public Include File for DRV2005 users
 *
 * Copyright (C) 2002 NxtWave Communications, Inc.
 *
 * $Log:   //panxtbdc01/AppsEng/PVCS/Application Eval/archives/EVAL2005/Include_new/drv2005.h-arc  $
 * 
 *    Rev 1.7   May 20 2003 18:12:34   raggarwa
 * Updated comments for NxtGetRdcStatus and NxtCoreControl
 * 
 *    Rev 1.6   May 01 2003 16:29:00   raggarwa
 * Fixed the function prototype for NxtSetMpegMode( )
 * 
 *    Rev 1.5   Mar 26 2003 10:52:12   raggarwa
 * Cleaned up comments
 * 
 *    Rev 1.4   Mar 25 2003 15:16:52   raggarwa
 * Updated comments
 * 
 *    Rev 1.3   Mar 19 2003 10:18:36   raggarwa
 * Updated comments
 * 
 *    Rev 1.2   Jan 21 2003 16:58:08   raggarwa
 * Updated comments for NxtSetAdcInputGain() API
 * 
 *    Rev 1.1   Jan 16 2003 17:28:10   raggarwa
 * Updated comments of NxtOutputControl()
 * 
 *    Rev 1.0   Jan 03 2003 11:42:58   raggarwa
 * Initial revision.
 * 
 *    Rev 1.1   Nov 06 2002 11:34:08   raggarwa
 * Changed AGC data  token values
 * 
 *    Rev 1.0   Nov 04 2002 14:03:20   raggarwa
 * Initial revision.
 * 
 *    Rev 1.30   Jun 11 2002 16:28:56   raggarwal
 * Added NXT_XTAL_FREQ;
 * Removed NxtRdcControlMode_t;
 * Added RDC Symbol Rates;
 * Changed NxtSetRdcSerialMode( );
 * Updated Comments
 * 
 *    Rev 1.29   May 17 2002 14:42:36   raggarwal
 * Updated comments
 * 
 *    Rev 1.28   May 10 2002 16:00:46   raggarwal
 * Added NxtOutputControl( ) API;
 * Added type to NxtControl_t;
 * Updated comments;
 * Fixed indentation style
 * 
 *    Rev 1.27   May 07 2002 15:44:32   raggarwal
 * Added headers for RDC related  API
 * 
 *    Rev 1.26   Apr 30 2002 14:16:30   raggarwal
 * Added RDC related enums
 * 
 *    Rev 1.25   Apr 18 2002 10:57:40   raggarwal
 * Changed pFdcSqi from Data32 to double
 * 
 *    Rev 1.24   Apr 15 2002 17:29:04   raggarwal
 * Added NxtControl_t
 * 
 *    Rev 1.23   Apr 11 2002 15:11:32   raggarwal
 * Updated comments
 * 
 *    Rev 1.22   Apr 08 2002 14:23:52   raggarwal
 * Changed NxtReturn_t to Data16
 * 
 *    Rev 1.21   Apr 08 2002 12:17:52   raggarwal
 * Updated comments
 * 
 *    Rev 1.20   Apr 03 2002 16:53:20   raggarwal
 * Added NxtSetFdcDecoderMode( )
 * 
 *    Rev 1.19   Mar 28 2002 14:34:30   raggarwal
 * Removed NXT_AGC_SETUP_ADJ from drv2005.h
 * 
 *    Rev 1.18   Mar 28 2002 13:49:20   raggarwal
 * Changed value of core_soft_reset_smoother
 * 
 *    Rev 1.17   Mar 26 2002 16:33:48   raggarwal
 * Changed Data8 *pFat/FdcAgcData  to Data16 *pFat/FdcAgcData
 * 
 *    Rev 1.16   Mar 22 2002 11:13:36   raggarwal
 * Renamed NXT_FDC_SYMBOL_RATE
 * 
 *    Rev 1.15   Mar 20 2002 13:49:32   raggarwal
 * Ended file with a carraige return
 * 
 *    Rev 1.14   Mar 18 2002 15:12:12   raggarwal
 * Updated comments
 * 
 *    Rev 1.13   Mar 15 2002 16:42:48   raggarwal
 * Updated comments
 * 
 *    Rev 1.12   Mar 13 2002 14:56:12   raggarwal
 * Renamed variable types
 * 
 *    Rev 1.11   Mar 08 2002 13:29:52   raggarwal
 * Got rid of NXT_LOAD_SCRIPT; Updated Comments
 * 
 *    Rev 1.10   Mar 06 2002 17:38:58   raggarwal
 * Removed NXT_INT_TAP and _SPECTRUM
 * 
 *    Rev 1.9   Mar 06 2002 16:55:26   raggarwal
 * Updated comments
 * 
 *    Rev 1.8   Mar 05 2002 10:45:32   raggarwal
 * Updated comments
 * 
 *    Rev 1.7   Feb 28 2002 18:45:58   raggarwal
 * Changed NxtCoreControl_t enum;
 * Updated comments
 * 
 *    Rev 1.6   Feb 26 2002 16:53:06   raggarwal
 * Updated comments
 * 
 *    Rev 1.5   Feb 25 2002 11:17:38   raggarwal
 * Moved NxtAcqOptions masks from enum to #defines
 * 
 *    Rev 1.4   Feb 22 2002 14:24:10   raggarwal
 * Removed NXT_SCRIPT_SIZE
 * 
 *    Rev 1.3   Feb 21 2002 16:46:36   raggarwal
 * Added FEC and EQ registers
 * 
 *    Rev 1.2   Feb 19 2002 17:16:22   raggarwal
 * Removed NxtGetFatPilotOffset( );
 * Added comments
 * 
 *    Rev 1.1   Feb 18 2002 15:00:52   raggarwal
 * Added NxtSetAdcInputGain( )
 * 
 *    Rev 1.0   Feb 13 2002 11:02:48   raggarwal
 * Initial revision.
 * 
 **********************************************************************/

#ifndef DRV2005_H
#define DRV2005_H

/*
******************************************************************************
Defines
******************************************************************************
*/


#ifdef DRV200X_C
#define DRV2_API
#else
#define DRV2_API extern 	
#endif

#if 0//def _WINDOWS
#define DATA8_TO_DATA16(x)  (((Data16) (*(x)))<<8) | (((Data16) (*((x)+1))) & 0x00ff)
#define DATA8_TO_DATA32(x)  ((((Data32) DATA8_TO_DATA16(x))<<16) | (((Data32) DATA8_TO_DATA16((x)+2))) & 0x0000ffff)
#else
#define DATA8_TO_DATA16(x)  ((((Data16) (*(x)))<<8) | (((Data16) (*((x)+1))) & 0x00ff))
#define DATA8_TO_DATA32(x)  ((((Data32) DATA8_TO_DATA16(x))<<16) | ((((Data32) DATA8_TO_DATA16((x)+2))) & 0x0000ffff))
#endif

#define NEGATE(x) ((~x)+1)
#define SIGN_EXT(x,len) (((x) & ((Data32)1 << (len-1))) ? ((x) | ((Data32)-1 << (len-1) )) : ((Data32)x))


#define	NXT_CRYSTAL_FREQ		25.14	/* MHz */

#define AGC_RAM_SIZE			192

/* Download/Upload maximum block transfer size */
#define MAX_XFER_BLOCK_SIZE		255

/* Maximum number of download attempts with crc error */
#define MAX_DNLD_TRIES			3

#define RAM_BASE_ROM_ENABLED	0x1000
#define RAM_BASE_ROM_DISABLED	0x0000
#define	UC_RAM_SIZE				0xA000
#define DI_RAM_END				0xFDFF


/* Interrupt Mask/Source Values */
#define NXT_INT_FAT_LOCK		0x80
#define NXT_INT_FAT_LOSS		0x40
#define NXT_INT_NTSC			0x20
#define NXT_INT_XFER			0x10
#define NXT_INT_FDC_LOCK		0x02
#define NXT_INT_FDC_LOSS		0x01


/* Interrupt Result/Status Values */
#define NXT_NTSC_DETECTED		0x01
#define NXT_XFER_ERROR			0x02


/* Acquisition Start/Stop Masks*/
#define	NXT_START_NO_CO_MASK	0x0400	/* bit to disable co-channel */
#define	NXT_START_ADJ_MASK		0x0800	/* bit to enable adjacent detection */
#define	NXT_START_CHANNEL_MASK	0xF000
#define	NXT_STOP_OPTIONS_MASK	0x00E0
#define	NXT_STOP_ASYNC_MASK		0x0020


/* AGC Setup Script Token Values */
#define NXT_AGC_SETUP_DONE		-1	/* end of agc setup data */
#define NXT_AGC_SETUP_64QAM		-2	/* start of 64Qam modifications */
#define NXT_AGC_SETUP_256QAM	-3	/* start of 256Qam modifications */
#define	NXT_FAT_AGC_SETUP_ADJ	-4	/* start of fat adj channel modifications */
#define NXT_AGC_IF_THRESHOLD	-5	/* start of FAT IF input thresholds */
#define NXT_AGC_RF_THRESHOLD	-6	/* start of FAT RF input thresholds */
#define NXT_FDC_AGC_SETUP_ADJ	-7	/* start of fdc adj channel modifications */
#define NXT_AGC_TOP_SETUP_8VSB      -8	/* 8-VSB Active Tracking_2 State machine setups */
#define NXT_AGC_TOP_SETUP_64QAM     -9  /* 64-QAM Active Tracking_2 State machine setups */
#define NXT_AGC_TOP_SETUP_256QAM   -10  /* 256-QAM Active Tracking_2 State machine setups */


/* API Return Error Codes */
#define	NXT_NO_ERROR        0
#define NXT_ERR_INIT        1	/* driver not initialized						*/
#define	NXT_ERR_RANGE       2	/* input parameter out-of-range					*/
#define	NXT_ERR_RESET       4	/* chip held in reset - output data invalid		*/
#define	NXT_ERR_MODE        8	/* current mode invalid for requested API		*/
#define	NXT_ERR_NO_LOCK    16	/* no frame/mpeg lock - output data invalid		*/
#define	NXT_ERR_MEMORY     32	/* failed to allocate memory for device context */
#define	NXT_ERR_OS         64	/* operating system call returned error			*/
#define	NXT_ERR_COMM      128	/* communication failure with NXT2005			*/
#define	NXT_ERR_OTHER     256	/* other error (unsupported, etc.)				*/
#define	NXT_ERR_TIMEOUT   512	/* service timed out							*/
#define	NXT_ERR_IIC_XFER  1024	/* Nxt2005 reported IIC Xfer failure			*/
#define	NXT_ERR_NOT_READY 2048	/* chip/data not ready for requested API		*/


/*
******************************************************************************
Public Types
******************************************************************************
*/

typedef enum {
  NXT_UNDEF_ASIC = 0x0,
  NXT_2003_ASIC,
  NXT_2004_ASIC,
  NXT_2005_ASIC
} NxtAsicType_t;

/* Acquisition Options */
typedef enum {
	NXT_DIRECT_TUNE					= 0,
	/* Start Options */
	NXT_CONFIG_8VSB					= 0x8000,
	NXT_CONFIG_8VSB_NO_CO			= 0x8400,
	NXT_CONFIG_8VSB_ADJ				= 0x8800,
	NXT_CONFIG_8VSB_ADJ_NO_CO		= 0x8C00,
	NXT_CONFIG_64QAM				= 0x4000,
	NXT_CONFIG_256QAM				= 0x2000,
	NXT_CONFIG_CABLE				= 0xE000,	/* 64QAM, 256QAM, 8VSB in that order */
	NXT_CONFIG_FDC					= 0x1000,
	NXT_ACTIVE_TRACKING_FAT			= 0x0200,
	NXT_ACTIVE_TRACKING_FDC			= 0x0100,
	NXT_ACTIVE_TRACKING_FAT_TOP		= 0x0002,
    NXT_START_NO_DELAY              = 0x0001,   /* return without any acquisition delay */
	/* Stop Options */
	NXT_STOP_FAT					= 0x0080,
	NXT_STOP_FDC					= 0x0040,
	NXT_STOP_FAT_FDC				= 0x00C0,
	NXT_STOP_FAT_ASYNC				= 0x00A0,
	NXT_STOP_FDC_ASYNC				= 0x0060,
	NXT_STOP_FAT_FDC_ASYNC			= 0x00E0
} NxtAcqOptions_t;

/* Read (upload) type */
typedef enum {
	NXT_READ_UC_RAM,
	NXT_READ_AGC_RAM
} NxtReadType_t;

/* Download Type */
typedef enum {
	NXT_LOAD_CODE = 0,
	NXT_LOAD_AGC = 2,
	NXT_LOAD_OTHER = 3
} NxtLoadType_t;

/* Signal Status */
typedef enum {
	NXT_SIG_NO_SIGNAL,
	NXT_SIG_WEAK,
	NXT_SIG_MODERATE,
	NXT_SIG_STRONG,
	NXT_SIG_VERY_STRONG
} NxtSignalState_t;

/* In-band Modulation Formats */
typedef enum {
	NXT_256QAM,
	NXT_64QAM,
	NXT_16VSB,
	NXT_8VSB
} NxtModFormat_t;

typedef enum {
    UNKNOWN = 0,
    VLOW_INPUT_LEVEL,      /*  Vrf & Vif at max */
    LOW_INPUT_LEVEL,       /*  Input level is < TOP (Vrf at max) */
    MED_INPUT_LEVEL,       /*  Input level is > TOP */
    MED_INPUT_LEVEL_INT,   /*  Input level is > TOP - with interference */
    MED_INPUT_LEVEL_INT2,  /*  Vif at max - with interference */
    HIGH_INPUT_LEVEL,      /*  Vrf at min */
    VHIGH_INPUT_LEVEL      /*  Vif & Vrf at min */
} MTAGCStates_t;

/* IIC Bypass Modes */
typedef enum {
	NXT_IIC_BYPASS,
	NXT_IIC_UC_CONTROL
} NxtBypass_t;

/* IIC Transfer Modes */
typedef enum {
	NXT_IIC_READ,
	NXT_IIC_WRITE
} NxtIicXferMode_t;

/* IIC Transfer Speeds */
enum {
	NXT_IIC_SPEED_FASTEST	= 0x00,	/* approx. 238 KHz */
	NXT_IIC_SPEED_STANDARD	= 0x03,	/* approx. 100 KHz */
	NXT_IIC_SPEED_SLOWEST	= 0x7F	/* approx. 4.8 KHz */
};

/* Polarities */
typedef enum {
	NON_INVERTED,
	INVERTED
} NxtPolarity_t;

/* Code Version */
typedef struct {
	Data8 major;
	Data8 custom;
	Data8 minor;
} CodeVersion_s;

/* ASIC Version */
typedef struct {
	Data8 device;
	Data8 fab;
	Data8 month;
	Data8 year[2];
} AsicVersion_s;

/* GPIO Control Modes */
typedef enum {
	NXT_GPIO_ASSIGN			= 0xC0,
	NXT_GPIO_SET_IO			= 0x80,
	NXT_GPIO_WRITE			= 0x40,
	NXT_GPIO_READ			= 0x00
} NxtGpioMode_t;

/* These controls are used for NxtCoreControl() */
typedef enum {
	CORE_POWER_DOWN_ALL	= 0x70,		/* power down all cores */
	CORE_POWER_UP_ALL	= 0x71,		/* power up all cores */
	CORE_POWER_UP_FAT	= 0x12,		/* power up FAT */
	CORE_POWER_DOWN_FAT	= 0x13,		/* power down FAT */
	CORE_POWER_UP_FDC	= 0x24,		/* power up FDC */
	CORE_POWER_DOWN_FDC	= 0x25,		/* power down FDC */
	CORE_POWER_UP_RDC	= 0x46,		/* power up RDC */
	CORE_POWER_DOWN_RDC	= 0x47,		/* power down RDC */
	CORE_SOFT_RESET_ALL		= 0x78,	/* soft reset FAT, FDC and RDC cores - cleared by driver */
	CORE_SOFT_RESET_BERT	= 0x39,	/* soft reset BERT - cleared by driver */
	CORE_SOFT_RESET_RDC		= 0x4A,	/* soft reset RDC - cleared by driver */
	CORE_SOFT_RESET_SMOOTHER= 0x1B,	/* soft reset MPEG output smoother - cleared by driver */
	CORE_SOFT_RESET_FAT_AGC	= 0x1C,	/* soft reset FAT AGC - cleared by driver */
	CORE_SOFT_RESET_FDC		= 0x2D,	/* soft reset FDC core - cleared by driver */
	CORE_SOFT_RESET_FDC_XAGC= 0x2E	/* soft reset FDC external AGC - cleared by driver */
} NxtCoreControl_t;

/* FDC symbol rates */
typedef enum {
	NXT_FDC_SYMBOL_RATE_772		= 0x00,
	NXT_FDC_SYMBOL_RATE_1024	= 0x80,
	NXT_FDC_SYMBOL_RATE_1544	= 0x40
} NxtFdcSymbolRate_t;