📄 panel.c
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#include "board.h"
#include "chip/compat.h"
#include "DrvGlobal.h"
#include "Panel.h"
#include "analog_reg.h"
#define DBG_PANEL(x) //x
#define USE_PANEL_DEFINE 1
#if (PANEL_TYPE_SEL == Pnl_AU07_AT)
#include "Pnl_AU07_AT.c"
#elif (PANEL_TYPE_SEL == Pnl_CPT07_DT)
#include "Pnl_CPT07_DT.c"
#elif (PANEL_TYPE_SEL == Pnl_TMD07_DT)
#include "Pnl_TMD07_DT.c"
#elif (PANEL_TYPE_SEL == Pnl_CPT07_AT)
#include "Pnl_CPT07_AT.c"
#elif (PANEL_TYPE_SEL == Pnl_AU07_DT)// kevin 071217
#include "Pnl_AU07_DT.c"
#elif (PANEL_TYPE_SEL == Pnl_CMO20_VGA)// kevin 080102
#include "Pnl_CMO20_VGA.c"
#elif (PANEL_TYPE_SEL == Pnl_AU20_WXGA)// kevin 080114
#include "Pnl_AU20_WXGA.c"
#elif (PANEL_TYPE_SEL == Pnl_CPT20_VGA)// kevin 080114
#include "Pnl_CPT20_VGA.c"
#elif (PANEL_TYPE_SEL == Pnl_TMD133_WXGA)// kevin 080114
#include "Pnl_TMD133_WXGA.c"
#else
#error "PANEL_TYPE_SEL(*.C) is wrong"
#endif
#if (KEEP_UNUSED_FUNC == 1)
PanelType code tPanelSXGA[] =
{
{
{"AU17EN05"},//m_pPanelName
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
0, //BOOL m_bPanelDither :1; //PANEL_DITHER // 8/6 bits panel
LINK_LVDS, //BOOL m_ePanelLinkType :2; //PANEL_LINK
1, //BOOL m_bPanelDualPort :1; //PANEL_DUAL_PORT
1, //BOOL m_bPanelSwapPort :1; //PANEL_SWAP_PORT
0, //BOOL m_bPanelSwapOdd_ML :1; //PANEL_SWAP_ODD_ML
0, //BOOL m_bPanelSwapEven_ML :1; //PANEL_SWAP_EVEN_ML
0, //BOOL m_bPanelSwapOdd_RB :1; //PANEL_SWAP_ODD_RB
0, //BOOL m_bPanelSwapEven_RB :1; //PANEL_SWAP_EVEN_RB
0, //BOOL m_bPanelSwapLVDS_POL :1; //PANEL_SWAP_LVDS_POL
0, //BOOL m_bPanelSwapLVDS_CH :1; //PANEL_SWAP_LVDS_CH
1, //BOOL m_bPanelLVDS_TI_MODE :1; //PANEL_LVDS_TI_MODE
0x00, //BYTE m_ucPanelDCLKDelay; //PANEL_DCLK_DELAY
0, //BOOL m_bPanelInvDCLK :1; //PANEL_INV_DCLK
0, //BOOL m_bPanelInvDE :1; //PANEL_INV_DE
0, //BOOL m_bPanelInvHSync :1; //PANEL_INV_HSYNC
0, //BOOL m_bPanelInvVSync :1; //PANEL_INV_VSYNC
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
0x01, //BYTE m_ucPanelDCKLCurrent; //PANEL_DCLK_CURRENT // DCLK current
0x01, //BYTE m_ucPanelDECurrent; //PANEL_DE_CURRENT // DE signal current
0x01, //BYTE m_ucPanelODDDataCurrent; //PANEL_ODD_DATA_CURRENT // odd data current
0x01, //BYTE m_ucPanelEvenDataCurrent; //PANEL_EVEN_DATA_CURRENT // even data current
10, //BYTE m_ucPanelOnTiming1; //PANEL_ON_TIMING1 // time between panel & data while turn on power
250, //BYTE m_ucPanelOnTiming2; //PANEL_ON_TIMING2 // time between data & back light while turn on power
100, //BYTE m_ucPanelOffTiming1; //PANEL_OFF_TIMING1 // time between back light & data while turn off power
10, //BYTE m_ucPanelOffTiming2; //PANEL_OFF_TIMING2 // time between data & panel while turn off power
32, //BYTE m_ucPanelHSyncWidth; //PANEL_HSYNC_WIDTH
24, //BYTE m_ucPanelHSyncBackPorch; //PANEL_HSYNC_BACK_PORCH
2, //BYTE m_ucPanelVSyncWidth; //PANEL_VSYNC_WIDTH
38, //BYTE m_ucPanelBackPorch; //PANEL_VSYNC_BACK_PORCH
32+24, //WORD m_wPanelHStart; //PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH-1)
2+38, //WORD m_wPanelVStart; //PANEL_VSTART (PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
1280, //WORD m_wPanelWidth; //PANEL_WIDTH
1024, //WORD m_wPanelHeight; //PANEL_HEIGHT
1800, //WORD m_wPanelMaxHTotal; //PANEL_MAX_HTOTAL
1688, //WORD m_wPanelHTotal; //PANEL_HTOTAL
1664, //WORD m_wPanelMinHTotal; //PANEL_MIN_HTOTAL
2047, //WORD m_wPanelMaxVTotal; //PANEL_MAX_VTOTAL
1066, //WORD m_wPanelVTotal; //PANEL_VTOTAL
1035, //WORD m_wPanelMinVTotal; //PANEL_MIN_VTOTAL
140, //DWORD m_dwPanelMaxDCLK; //PANEL_MAX_DCLK
108, //DWORD m_dwPanelDCLK; //PANEL_DCLK
100, //DWORD m_dwPanelMinDCLK; //PANEL_MIN_DCLK
0x0019, //m_wSpreadSpectrumStep; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0x00EC, //m_wSpreadSpectrumSpan; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
117, //m_ucDimmingCtl
255, //m_ucMaxPWMVal;
63, //m_ucMinPWMVal;
0, //BOOL m_bPanelDeinterMode :1; //PANEL_DEINTER_MODE
},
};//
PanelType code tPanelWXGA[] =
{
{//Auo20" T200XW02V0
"AU20_T200XW02",//m_pPanelName
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
0, //BOOL m_bPanelDither :1; //PANEL_DITHER // 8/6 bits panel
LINK_LVDS, //BOOL m_ePanelLinkType :2; //PANEL_LINK
0, //BOOL m_bPanelDualPort :1; //PANEL_DUAL_PORT
0, //BOOL m_bPanelSwapPort :1; //PANEL_SWAP_PORT
0, //BOOL m_bPanelSwapOdd_ML :1; //PANEL_SWAP_ODD_ML
0, //BOOL m_bPanelSwapEven_ML :1; //PANEL_SWAP_EVEN_ML
0, //BOOL m_bPanelSwapOdd_RB :1; //PANEL_SWAP_ODD_RB
0, //BOOL m_bPanelSwapEven_RB :1; //PANEL_SWAP_EVEN_RB
0, //BOOL m_bPanelSwapLVDS_POL :1; //PANEL_SWAP_LVDS_POL
0, //BOOL m_bPanelSwapLVDS_CH :1; //PANEL_SWAP_LVDS_CH
1, //BOOL m_bPanelLVDS_TI_MODE :1; //PANEL_LVDS_TI_MODE
0x00, //BYTE m_ucPanelDCLKDelay; //PANEL_DCLK_DELAY
0, //BOOL m_bPanelInvDCLK :1; //PANEL_INV_DCLK
0, //BOOL m_bPanelInvDE :1; //PANEL_INV_DE
0, //BOOL m_bPanelInvHSync :1; //PANEL_INV_HSYNC
0, //BOOL m_bPanelInvVSync :1; //PANEL_INV_VSYNC
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
0x01, //BYTE m_ucPanelDCKLCurrent; //PANEL_DCLK_CURRENT // DCLK current
0x01, //BYTE m_ucPanelDECurrent; //PANEL_DE_CURRENT // DE signal current
0x01, //BYTE m_ucPanelODDDataCurrent; //PANEL_ODD_DATA_CURRENT // odd data current
0x01, //BYTE m_ucPanelEvenDataCurrent; //PANEL_EVEN_DATA_CURRENT // even data current
30, //45, //BYTE m_ucPanelOnTiming1; //PANEL_ON_TIMING1 // time between panel & data while turn on power
400, //BYTE m_ucPanelOnTiming2; //PANEL_ON_TIMING2 // time between data & back light while turn on power
20, //BYTE m_ucPanelOffTiming1; //PANEL_OFF_TIMING1 // time between back light & data while turn off power
10, //20, //BYTE m_ucPanelOffTiming2; //PANEL_OFF_TIMING2 // time between data & panel while turn off power
20, //BYTE m_ucPanelHSyncWidth; //PANEL_HSYNC_WIDTH
40, //BYTE m_ucPanelHSyncBackPorch; //PANEL_HSYNC_BACK_PORCH
4, //BYTE m_ucPanelVSyncWidth; //PANEL_VSYNC_WIDTH
34, //BYTE m_ucPanelBackPorch; //PANEL_VSYNC_BACK_PORCH
20+40, //WORD m_wPanelHStart; //PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
4+34, //WORD m_wPanelVStart; //PANEL_VSTART (PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
1366, //WORD m_wPanelWidth; //PANEL_WIDTH
768, //WORD m_wPanelHeight; //PANEL_HEIGHT
1606ul, //WORD m_wPanelMaxHTotal; //PANEL_MAX_HTOTAL
1430ul,//1560, //WORD m_wPanelHTotal; //PANEL_HTOTAL
1420ul, //WORD m_wPanelMinHTotal; //PANEL_MIN_HTOTAL
840, //WORD m_wPanelMaxVTotal; //PANEL_MAX_VTOTAL
789ul, //WORD m_wPanelVTotal; //PANEL_VTOTAL 20060511 chris :for Frame Lock operation
789, //WORD m_wPanelMinVTotal; //PANEL_MIN_VTOTAL
88, //DWORD m_dwPanelMaxDCLK; //PANEL_MAX_DCLK
76, //DWORD m_dwPanelDCLK; //PANEL_DCLK
65, //DWORD m_dwPanelMinDCLK; //PANEL_MIN_DCLK
0x0000, //m_wSpreadSpectrumStep; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0x0000, //m_wSpreadSpectrumSpan; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0x7C, //m_ucDimmingCtl
255, //m_ucMaxPWMVal;
88,//63, //m_ucMinPWMVal;
0, //BOOL m_bPanelDeinterMode :1; //PANEL_DEINTER_MODE
},
};//!<Panel Data 历厘 备炼眉.(Multi Panel 措览阑 困秦 荤侩)
PanelType code tPanelWXGAPLUS[] =
{
{//CMO 19" M190A1-L02
"M190A1",//m_pPanelName
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
0, //BOOL m_bPanelDither :1; //PANEL_DITHER // 8/6 bits panel
LINK_LVDS, //BOOL m_ePanelLinkType :2; //PANEL_LINK
1, //BOOL m_bPanelDualPort :1; //PANEL_DUAL_PORT
0, //BOOL m_bPanelSwapPort :1; //PANEL_SWAP_PORT
0, //BOOL m_bPanelSwapOdd_ML :1; //PANEL_SWAP_ODD_ML
0, //BOOL m_bPanelSwapEven_ML :1; //PANEL_SWAP_EVEN_ML
0, //BOOL m_bPanelSwapOdd_RB :1; //PANEL_SWAP_ODD_RB
0, //BOOL m_bPanelSwapEven_RB :1; //PANEL_SWAP_EVEN_RB
1, //BOOL m_bPanelSwapLVDS_POL :1; //PANEL_SWAP_LVDS_POL
1, //BOOL m_bPanelSwapLVDS_CH :1; //PANEL_SWAP_LVDS_CH
1, //BOOL m_bPanelLVDS_TI_MODE :1; //PANEL_LVDS_TI_MODE
0x00, //BYTE m_ucPanelDCLKDelay; //PANEL_DCLK_DELAY
0, //BOOL m_bPanelInvDCLK :1; //PANEL_INV_DCLK
0, //BOOL m_bPanelInvDE :1; //PANEL_INV_DE
0, //BOOL m_bPanelInvHSync :1; //PANEL_INV_HSYNC
0, //BOOL m_bPanelInvVSync :1; //PANEL_INV_VSYNC
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
0x01, //BYTE m_ucPanelDCKLCurrent; //PANEL_DCLK_CURRENT // DCLK current
0x01, //BYTE m_ucPanelDECurrent; //PANEL_DE_CURRENT // DE signal current
0x01, //BYTE m_ucPanelODDDataCurrent; //PANEL_ODD_DATA_CURRENT // odd data current
0x01, //BYTE m_ucPanelEvenDataCurrent; //PANEL_EVEN_DATA_CURRENT // even data current
30, //BYTE m_ucPanelOnTiming1; //PANEL_ON_TIMING1 // time between panel & data while turn on power
500, //BYTE m_ucPanelOnTiming2; //PANEL_ON_TIMING2 // time between data & back light while turn on power
100, //BYTE m_ucPanelOffTiming1; //PANEL_OFF_TIMING1 // time between back light & data while turn off power
40, //BYTE m_ucPanelOffTiming2; //PANEL_OFF_TIMING2 // time between data & panel while turn off power
30, //BYTE m_ucPanelHSyncWidth; //PANEL_HSYNC_WIDTH
30, //BYTE m_ucPanelHSyncBackPorch; //PANEL_HSYNC_BACK_PORCH
6, //BYTE m_ucPanelVSyncWidth; //PANEL_VSYNC_WIDTH
2, //BYTE m_ucPanelBackPorch; //PANEL_VSYNC_BACK_PORCH
30+30, //WORD m_wPanelHStart; //PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
6+2, //WORD m_wPanelVStart; //PANEL_VSTART (PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
1440, //WORD m_wPanelWidth; //PANEL_WIDTH
900, //WORD m_wPanelHeight; //PANEL_HEIGHT
1920, //WORD m_wPanelMaxHTotal; //PANEL_MAX_HTOTAL
1600, //WORD m_wPanelHTotal; //PANEL_HTOTAL
1500, //WORD m_wPanelMinHTotal; //PANEL_MIN_HTOTAL
1050, //WORD m_wPanelMaxVTotal; //PANEL_MAX_VTOTAL
926, //WORD m_wPanelVTotal; //PANEL_VTOTAL 20060511 chris :for Frame Lock operation
905, //WORD m_wPanelMinVTotal; //PANEL_MIN_VTOTAL
(2*56), //DWORD m_dwPanelMaxDCLK; //PANEL_MAX_DCLK
(2*44), //DWORD m_dwPanelDCLK; //PANEL_DCLK
(2*36), //DWORD m_dwPanelMinDCLK; //PANEL_MIN_DCLK
0x003F,//0x0010, //m_wSpreadSpectrumStep; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0x0100, //m_wSpreadSpectrumSpan; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0xFF, //m_ucDimmingCtl
255, //m_ucMaxPWMVal;
88,//63, //m_ucMinPWMVal;
0, //BOOL m_bPanelDeinterMode :1; //PANEL_DEINTER_MODE
},
};
PanelType code tPanelWSXGA[] =
{
{//CMO22" M220Z1-L01
"M220Z1",//m_pPanelName
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
0, //BOOL m_bPanelDither :1; //PANEL_DITHER // 8/6 bits panel
LINK_LVDS, //BOOL m_ePanelLinkType :2; //PANEL_LINK
1, //BOOL m_bPanelDualPort :1; //PANEL_DUAL_PORT
1, //BOOL m_bPanelSwapPort :1; //PANEL_SWAP_PORT
0, //BOOL m_bPanelSwapOdd_ML :1; //PANEL_SWAP_ODD_ML
0, //BOOL m_bPanelSwapEven_ML :1; //PANEL_SWAP_EVEN_ML
0, //BOOL m_bPanelSwapOdd_RB :1; //PANEL_SWAP_ODD_RB
0, //BOOL m_bPanelSwapEven_RB :1; //PANEL_SWAP_EVEN_RB
0, //BOOL m_bPanelSwapLVDS_POL :1; //PANEL_SWAP_LVDS_POL
0, //BOOL m_bPanelSwapLVDS_CH :1; //PANEL_SWAP_LVDS_CH
1, //BOOL m_bPanelLVDS_TI_MODE :1; //PANEL_LVDS_TI_MODE
0x00, //BYTE m_ucPanelDCLKDelay; //PANEL_DCLK_DELAY
0, //BOOL m_bPanelInvDCLK :1; //PANEL_INV_DCLK
0, //BOOL m_bPanelInvDE :1; //PANEL_INV_DE
0, //BOOL m_bPanelInvHSync :1; //PANEL_INV_HSYNC
0, //BOOL m_bPanelInvVSync :1; //PANEL_INV_VSYNC
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
0x01, //BYTE m_ucPanelDCKLCurrent; //PANEL_DCLK_CURRENT // DCLK current
0x01, //BYTE m_ucPanelDECurrent; //PANEL_DE_CURRENT // DE signal current
0x01, //BYTE m_ucPanelODDDataCurrent; //PANEL_ODD_DATA_CURRENT // odd data current
0x01, //BYTE m_ucPanelEvenDataCurrent; //PANEL_EVEN_DATA_CURRENT // even data current
20, //BYTE m_ucPanelOnTiming1; //PANEL_ON_TIMING1 // time between panel & data while turn on power
500, //BYTE m_ucPanelOnTiming2; //PANEL_ON_TIMING2 // time between data & back light while turn on power
120, //BYTE m_ucPanelOffTiming1; //PANEL_OFF_TIMING1 // time between back light & data while turn off power
20, //BYTE m_ucPanelOffTiming2; //PANEL_OFF_TIMING2 // time between data & panel while turn off power
18, //BYTE m_ucPanelHSyncWidth; //PANEL_HSYNC_WIDTH
50, //BYTE m_ucPanelHSyncBackPorch; //PANEL_HSYNC_BACK_PORCH
8, //BYTE m_ucPanelVSyncWidth; //PANEL_VSYNC_WIDTH
8, //BYTE m_ucPanelBackPorch; //PANEL_VSYNC_BACK_PORCH
18+50, //WORD m_wPanelHStart; //PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
8+8, //WORD m_wPanelVStart; //PANEL_VSTART (PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
1680, //WORD m_wPanelWidth; //PANEL_WIDTH
1050, //WORD m_wPanelHeight; //PANEL_HEIGHT
2000, //WORD m_wPanelMaxHTotal; //PANEL_MAX_HTOTAL
1840, //WORD m_wPanelHTotal; //PANEL_HTOTAL
1780, //WORD m_wPanelMinHTotal; //PANEL_MIN_HTOTAL
1195, //WORD m_wPanelMaxVTotal; //PANEL_MAX_VTOTAL
1080, //WORD m_wPanelVTotal; //PANEL_VTOTAL 20060511 chris :for Frame Lock operation
1060, //WORD m_wPanelMinVTotal; //PANEL_MIN_VTOTAL
(150), //DWORD m_dwPanelMaxDCLK; //PANEL_MAX_DCLK
(119), //DWORD m_dwPanelDCLK; //PANEL_DCLK
(110), //DWORD m_dwPanelMinDCLK; //PANEL_MIN_DCLK
0x0001, //0x0010, //m_wSpreadSpectrumStep; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0x0001, //m_wSpreadSpectrumSpan; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
0xFF, //0x87, //m_ucDimmingCtl
255, //m_ucMaxPWMVal;
88,//63, //m_ucMinPWMVal;
0, //BOOL m_bPanelDeinterMode :1; //PANEL_DEINTER_MODE
},
};
PanelType code * tPanelIndexTbl[] =
{
& tPanelSXGA,
& tPanelWXGA,
& tPanelWXGAPLUS, //1440*900 //CHR_060912_1 Resolution 眠啊
& tPanelWSXGA, //1680*1050
};
#endif
#if (KEEP_UNUSED_FUNC == 1)
U8 * pnlGetPanelName(void)
{
PanelType * pPanelData;
pPanelData = tPanelIndexTbl[stGenSetting.g_SysSetting.enPanelResType];
pPanelData += stGenSetting.g_SysSetting.u8PanelModel;
return pPanelData->m_pPanelName;
}
#endif
BOOLEAN pnlGetDitherEnable()
{
#if (USE_PANEL_DEFINE == 1)
return PANEL_DITHER;
#else
PanelType * pPanelData;
pPanelData = tPanelIndexTbl[stGenSetting.g_SysSetting.enPanelResType];
pPanelData += stGenSetting.g_SysSetting.u8PanelModel;
return pPanelData->m_bPanelDither;
#endif
}
PANEL_LINK_TYPE pnlGetLinkType(void)
{
#if (USE_PANEL_DEFINE == 1)
return LINK_LVDS;
#else
PanelType * pPanelData;
pPanelData = tPanelIndexTbl[stGenSetting.g_SysSetting.enPanelResType];
pPanelData += stGenSetting.g_SysSetting.u8PanelModel;
return pPanelData->m_ePanelLinkType;
#endif
}
BOOLEAN pnlGetDualPortEnable(void)
{
#if (USE_PANEL_DEFINE == 1)
return PANEL_DUAL_PORT;
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