📄 panel.h
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#ifndef _PANEL_H_
#define _PANEL_H_
#include "DataType.h"
#include "board.h"
////////////////////////////////////////////////////
// Include the real header file
////////////////////////////////////////////////////
#if (PANEL_TYPE_SEL == Pnl_AU07_AT)
#include "Pnl_AU07_AT.h"
#elif (PANEL_TYPE_SEL == Pnl_CPT07_DT)
#include "Pnl_CPT07_DT.h"
#elif (PANEL_TYPE_SEL == Pnl_TMD07_DT)
#include "Pnl_TMD07_DT.h"
#elif (PANEL_TYPE_SEL == Pnl_CPT07_AT)
#include "Pnl_CPT07_AT.h"
#elif (PANEL_TYPE_SEL == Pnl_AU07_DT)// kevin 071217
#include "Pnl_AU07_DT.h"
#elif (PANEL_TYPE_SEL == Pnl_CMO20_VGA)// kevin 080102
#include "Pnl_CMO20_VGA.h"
#elif (PANEL_TYPE_SEL == Pnl_AU20_WXGA)// kevin 080114
#include "Pnl_AU20_WXGA.h"
#elif (PANEL_TYPE_SEL == Pnl_CPT20_VGA)// kevin 080114
#include "Pnl_CPT20_VGA.h"
#elif (PANEL_TYPE_SEL == Pnl_TMD133_WXGA)// kevin 080114
#include "Pnl_TMD133_WXGA.h"
#else
#error "PANEL_TYPE_SEL(*.h) is wrong"
#endif
typedef enum
{
PANEL_RES_MIN,
PANEL_RES_VGA = PANEL_RES_MIN, //640 480
PANEL_RES_SVGA, //800 600
PANEL_RES_XGA, //1024 768
PANEL_RES_SXGA, //1280 1024
PANEL_RES_WXGA,
PANEL_RES_WXGA_PLUS,
PANEL_RES_WSXGA,
PANEL_RES_MAX,
PANEL_RES_MAX_NUM,
}PANEL_RESOLUTION_TYPE;
//lachesis_070125
typedef enum
{
LINK_TTL,
LINK_LVDS,
LINK_RSDS,
LINK_TCON,
LINK_ANALOG_TCON,
LINK_DIGITAL_TCON,
}PANEL_LINK_TYPE;
typedef struct
{
U8 *m_pPanelName; //m_pPanelName 10磊鳖扁 钎矫且 荐 乐澜.
//////////////////////////////////////////////
// Panel output
//////////////////////////////////////////////
U8 m_bPanelDither :1; //PANEL_DITHER 0 // 8/6 bits panel
PANEL_LINK_TYPE m_ePanelLinkType :4; //#define PANEL_LINK
U8 m_bPanelDualPort :1; //#define PANEL_DUAL_PORT 0
U8 m_bPanelSwapPort :1; //#define PANEL_SWAP_PORT 0
U8 m_bPanelSwapOdd_ML :1; //#define PANEL_SWAP_ODD_ML 0
U8 m_bPanelSwapEven_ML :1; //#define PANEL_SWAP_EVEN_ML 0
U8 m_bPanelSwapOdd_RB :1; //#define PANEL_SWAP_ODD_RB 0
U8 m_bPanelSwapEven_RB :1; //#define PANEL_SWAP_EVEN_RB 0
U8 m_bPanelSwapLVDS_POL :1; //#define PANEL_SWAP_LVDS_POL 0
U8 m_bPanelSwapLVDS_CH :1; //#define PANEL_SWAP_LVDS_CH 0
U8 m_bPanelLVDS_TI_MODE :1; //#define PANEL_LVDS_TI_MODE _PNL_FUNC_EN_
U8 m_ucPanelDCLKDelay; //#define PANEL_DCLK_DELAY 0x00
U8 m_bPanelInvDCLK :1; //#define PANEL_INV_DCLK 0
U8 m_bPanelInvDE :1; //#define PANEL_INV_DE 0
U8 m_bPanelInvHSync :1; //#define PANEL_INV_HSYNC 0
U8 m_bPanelInvVSync :1; //#define PANEL_INV_VSYNC 0
///////////////////////////////////////////////
// Output tmming setting
///////////////////////////////////////////////
// driving current setting (0x00=4mA, 0x01=6mA, 0x02=8mA, 0x03=12mA)
U8 m_ucPanelDCKLCurrent; //#define PANEL_DCLK_CURRENT 0x01 // DCLK current
U8 m_ucPanelDECurrent; //#define PANEL_DE_CURRENT 0x01 // DE signal current
U8 m_ucPanelODDDataCurrent; //#define PANEL_ODD_DATA_CURRENT 0x01 // odd data current
U8 m_ucPanelEvenDataCurrent; //#define PANEL_EVEN_DATA_CURRENT 0x01 // even data current
U16 m_ucPanelOnTiming1; //#define PANEL_ON_TIMING1 30 // time between panel & data while turn on power
U16 m_ucPanelOnTiming2; //#define PANEL_ON_TIMING2 100 // time between data & back light while turn on power
U16 m_ucPanelOffTiming1; //#define PANEL_OFF_TIMING1 20 // time between back light & data while turn off power
U16 m_ucPanelOffTiming2; //#define PANEL_OFF_TIMING2 20 // time between data & panel while turn off power
U8 m_ucPanelHSyncWidth; //#define PANEL_HSYNC_WIDTH 32
U8 m_ucPanelHSyncBackPorch;//#define PANEL_HSYNC_BACK_PORCH 8
U8 m_ucPanelVSyncWidth; //#define PANEL_VSYNC_WIDTH 6
U8 m_ucPanelVBackPorch; //#define PANEL_VSYNC_BACK_PORCH 2
U16 m_wPanelHStart; //#define PANEL_HSTART (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)
U16 m_wPanelVStart; //#define PANEL_VSTART (PANEL_VSYNC_WIDTH + PANEL_VSYNC_BACK_PORCH)
U16 m_wPanelWidth; //#define PANEL_WIDTH 1366//1280
U16 m_wPanelHeight; //#define PANEL_HEIGHT 768
U16 m_wPanelMaxHTotal; //#define PANEL_MAX_HTOTAL
U16 m_wPanelHTotal; //#define PANEL_HTOTAL
U16 m_wPanelMinHTotal; //#define PANEL_MIN_HTOTAL
U16 m_wPanelMaxVTotal; //#define PANEL_MAX_VTOTAL
U16 m_wPanelVTotal; //#define PANEL_VTOTAL
U16 m_wPanelMinVTotal; //#define PANEL_MIN_VTOTAL
U8 m_dwPanelMaxDCLK; //#define PANEL_MAX_DCLK
U8 m_dwPanelDCLK; //#define PANEL_DCLK
U8 m_dwPanelMinDCLK; //#define PANEL_MIN_DCLK
//spread spectrum
U16 m_wSpreadSpectrumStep; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
U16 m_wSpreadSpectrumSpan; //Value for Spread_Spectrum_Control register(B7..3:Period,B2..0:Amplitude)
U8 m_ucDimmingCtl;
U8 m_ucMaxPWMVal;
U8 m_ucMinPWMVal;
U8 m_bPanelDeinterMode :1; //#define PANEL_DEINTER_MODE
} PanelType;
#ifndef PANEL_SYNC_MODE_1
#define PANEL_SYNC_MODE_1 0
#endif
#ifndef PANEL_ATCON
#define PANEL_ATCON 0
#endif
#ifndef ENABLE_DPWM_FUNCTION
#define ENABLE_DPWM_FUNCTION 0
#endif
#ifndef ENABLE_DPWM_LED
#define ENABLE_DPWM_LED 0
#endif
#ifndef DPWM_BURST_MODE
#define DPWM_BURST_MODE 0
#endif
#ifndef DISABLE_SHORT_FRAME_TUNE
#define DISABLE_SHORT_FRAME_TUNE 1
#endif
#ifndef DISABLE_SHORT_LINE_TUNE
#define DISABLE_SHORT_LINE_TUNE 0
#endif
#ifndef SET_SSC_SPAN
#define SET_SSC_SPAN 0x00
#endif
#ifndef SET_SSC_STEP
#define SET_SSC_STEP 0x00
#endif
#ifndef PANEL_DOT_HEIGHT
#define PANEL_DOT_HEIGHT 100
#endif
#ifndef PANEL_DOT_WIDTH
#define PANEL_DOT_WIDTH PANEL_DOT_HEIGHT
#endif
#ifndef CRT_INTERLACE_DOUBLOUT
#define CRT_INTERLACE_DOUBLOUT 0
#endif
#ifndef LVDS_CURRENT_LEVEL// BK30_42L[4:0]// kevin 080114_1
#define LVDS_CURRENT_LEVEL 0
#endif
#ifndef LVDS_CURRENT_LEVEL_DOUBLE// BK30_48L[4]// kevin 080114_1
#define LVDS_CURRENT_LEVEL_DOUBLE 0//_BIT4
#endif
#define WIDE_PANEL 0
#define _4_3_PANEL 1
#define OTHER_PANEL 2
#define _5_4_PANEL 3
#define _16_9_PANEL 4
////////////////////////////////////////////////////
// Panel common constant
////////////////////////////////////////////////////
#define PANEL_PWM_BRIGHT 1
#define PANEL_DE_VSTART 0
////////////////////////////////////////////////////
// Panel power sequence
////////////////////////////////////////////////////
//Truman temp
//#define pnlSetFPVCCOn() SetPinFpVcc()
//#define pnlSetFPVCCOff() ClrPinFpVcc()
////////////////////////////////////////////////////
// Ouput Clock PLL
////////////////////////////////////////////////////
// seven 070821
#define PANEL_LPLL_INPUT_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_INPUT_DIV_2nd 0x08 // can't set 0 and 1 , 2:x2 , 3:x3 , 4:x4 ...
#if (PANEL_ATCON)
#define PANEL_LPLL_LOOP_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#else
#define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8
#endif
#define PANEL_LPLL_LOOP_DIV_2nd 0x01 //
#define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_OUTPUT_DIV_2nd 0x00
#define PANEL_MPLL_M PANEL_LPLL_MM
//OutputClk = XTAL * MM * (524288 * LM * K / (SET * A))
// XTAL= external XTAL, 14.318MHz
// MM = LPLL diver LM, the recommended value is 8
// K = LPLL divder K, recommended setting is 1
// SET = LPLL divider SEET
// A = LPLL divider A, analog panel:7*3 , other:7*1
#define PANEL_LPLL_MM (((U32) 215000+(U32)MST_XTAL_CLOCK_KHZ/2)/(U32)MST_XTAL_CLOCK_KHZ)
#define PANEL_LPLL_LM (8>>PANEL_LPLL_INPUT_DIV_1st)
#define PANEL_LPLL_K (PANEL_LPLL_INPUT_DIV_2nd)
#if (PANEL_ATCON)
#define PANEL_LPLL_A (7*3)
#else
#define PANEL_LPLL_A 7
#endif
// end
#define PANEL_MPLL_LOOP_DIV2 PANEL_LPLL_MM
/*
#define PANEL_LPLL_INPUT_DIV_1st 0x00
#define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#if (PANEL_ATCON)
#define PANEL_LPLL_LOOP_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#else
#define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8
#endif
#define PANEL_LPLL_LOOP_DIV_2nd 0x01 //
#define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8
#define PANEL_LPLL_OUTPUT_DIV_2nd 0x00
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