📄 drvtvencoder.c
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{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_COEF_NTSC_TBL[] =
{// disable filter
{L_BK_VE_ENC(0x0F), 0x00},// lfir_coef1
{H_BK_VE_ENC(0x0F), 0x00},
{L_BK_VE_ENC(0x10), 0x00},// lfir_coef2
{H_BK_VE_ENC(0x10), 0x00},
{L_BK_VE_ENC(0x11), 0x00},// lfir_coef3
{H_BK_VE_ENC(0x11), 0x00},
{L_BK_VE_ENC(0x12), 0x00},// lfir_coef4
{H_BK_VE_ENC(0x12), 0x00},
{L_BK_VE_ENC(0x13), 0x00},// lfir_coef5
{H_BK_VE_ENC(0x13), 0x00},
{L_BK_VE_ENC(0x14), 0x00},// lfir_coef6
{H_BK_VE_ENC(0x14), 0x02},
{L_BK_VE_ENC(0x1A), 0x00},// cfir_coef1
{H_BK_VE_ENC(0x1A), 0x00},
{L_BK_VE_ENC(0x1B), 0x00},// cfir_coef2
{H_BK_VE_ENC(0x1B), 0x00},
{L_BK_VE_ENC(0x1C), 0x00},// cfir_coef3
{H_BK_VE_ENC(0x1C), 0x00},
{L_BK_VE_ENC(0x1D), 0x00},// cfir_coef4
{H_BK_VE_ENC(0x1D), 0x00},
{L_BK_VE_ENC(0x1E), 0x00},// cfir_coef5
{H_BK_VE_ENC(0x1E), 0x00},
{L_BK_VE_ENC(0x1F), 0x00},// cfir_coef6
{H_BK_VE_ENC(0x1F), 0x02},
{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_COEF_PAL_TBL[] =
{
{L_BK_VE_ENC(0x0F), 0x00},// lfir_coef1
{H_BK_VE_ENC(0x0F), 0x00},
{L_BK_VE_ENC(0x10), 0x00},// lfir_coef2
{H_BK_VE_ENC(0x10), 0x00},
{L_BK_VE_ENC(0x11), 0x00},// lfir_coef3
{H_BK_VE_ENC(0x11), 0x00},
{L_BK_VE_ENC(0x12), 0x00},// lfir_coef4
{H_BK_VE_ENC(0x12), 0x00},
{L_BK_VE_ENC(0x13), 0x00},// lfir_coef5
{H_BK_VE_ENC(0x13), 0x00},
{L_BK_VE_ENC(0x14), 0x00},// lfir_coef6
{H_BK_VE_ENC(0x14), 0x02},
{L_BK_VE_ENC(0x1A), 0x00},// cfir_coef1
{H_BK_VE_ENC(0x1A), 0x00},
{L_BK_VE_ENC(0x1B), 0x00},// cfir_coef2
{H_BK_VE_ENC(0x1B), 0x00},
{L_BK_VE_ENC(0x1C), 0x00},// cfir_coef3
{H_BK_VE_ENC(0x1C), 0x00},
{L_BK_VE_ENC(0x1D), 0x00},// cfir_coef4
{H_BK_VE_ENC(0x1D), 0x00},
{L_BK_VE_ENC(0x1E), 0x00},// cfir_coef5
{H_BK_VE_ENC(0x1E), 0x00},
{L_BK_VE_ENC(0x1F), 0x00},// cfir_coef6
{H_BK_VE_ENC(0x1F), 0x02},
{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_VBI_NTSC_TBL[] =
{
{L_BK_VE_ENC(0x2E), 0x00},// VBI mode
{H_BK_VE_ENC(0x2E), 0x00},
{L_BK_VE_ENC(0x4E), 0x15},// ccvbi_st1
{H_BK_VE_ENC(0x4E), 0x00},
{L_BK_VE_ENC(0x4F), 0x15},// ccvbi_end1
{H_BK_VE_ENC(0x4F), 0x00},
{L_BK_VE_ENC(0x50), 0x1C},// ccvbi_st2
{H_BK_VE_ENC(0x50), 0x01},
{L_BK_VE_ENC(0x51), 0x1C},// ccvbi_end2
{H_BK_VE_ENC(0x51), 0x01},
{L_BK_VE_ENC(0x56), 0x14},// wssvbi_st1
{H_BK_VE_ENC(0x56), 0x00},
{L_BK_VE_ENC(0x57), 0x14},// wssvbi_end1
{H_BK_VE_ENC(0x57), 0x00},
{L_BK_VE_ENC(0x6C), 0x1B},// wssvbi_st2
{H_BK_VE_ENC(0x6C), 0x01},
{L_BK_VE_ENC(0x6D), 0x1B},// wssvbi_end2
{H_BK_VE_ENC(0x6D), 0x01},
{L_BK_VE_ENC(0x5C), 0xD6},// cc_phs_step [15:0]
{H_BK_VE_ENC(0x5C), 0x1D},
{L_BK_VE_ENC(0x5D), 0xC6},// cc_phs_step [31:16]
{H_BK_VE_ENC(0x5D), 0x04},
{L_BK_VE_ENC(0x60), 0x84},// wws_phs_step [15:0]
{H_BK_VE_ENC(0x60), 0x0F},
{L_BK_VE_ENC(0x61), 0x3E},// wws_phs_step [31:16]
{H_BK_VE_ENC(0x61), 0x04},
{L_BK_VE_ENC(0x64), 0x10},// cc_st
{H_BK_VE_ENC(0x64), 0x01},
{L_BK_VE_ENC(0x66), 0x2E},// wws_st
{H_BK_VE_ENC(0x66), 0x01},
{L_BK_VE_ENC(0x68), 0x18},// cc_lvl
{H_BK_VE_ENC(0x68), 0x01},
{L_BK_VE_ENC(0x6A), 0x90},// wws_lvl
{H_BK_VE_ENC(0x6A), 0x01},
{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_VBI_PAL_TBL[] =
{
{L_BK_VE_ENC(0x2E), 0x00},// vbi mode
{H_BK_VE_ENC(0x2E), 0x00},
{L_BK_VE_ENC(0x52), 0x10},// vpsvib_st1
{H_BK_VE_ENC(0x52), 0x00},
{L_BK_VE_ENC(0x53), 0x10},// vpsvib_end1
{H_BK_VE_ENC(0x53), 0x00},
{L_BK_VE_ENC(0x54), 0x1C},// vpsvib_st2
{H_BK_VE_ENC(0x54), 0x01},
{L_BK_VE_ENC(0x55), 0x1B},// vpsvib_end2
{H_BK_VE_ENC(0x55), 0x01},
{L_BK_VE_ENC(0x56), 0x17},// wssvbi_st1
{H_BK_VE_ENC(0x56), 0x00},
{L_BK_VE_ENC(0x57), 0x17},// wssvbi_st2
{H_BK_VE_ENC(0x57), 0x00},
{L_BK_VE_ENC(0x6C), 0x1C},// wssvbi_st2
{H_BK_VE_ENC(0x6C), 0x01},
{L_BK_VE_ENC(0x6D), 0x1B},// wssvbi_st2
{H_BK_VE_ENC(0x6D), 0x01},
{L_BK_VE_ENC(0x58), 0x06},// ttvbi_st1
{H_BK_VE_ENC(0x58), 0x00},
{L_BK_VE_ENC(0x59), 0x16},// ttvbi_end1
{H_BK_VE_ENC(0x59), 0x00},
{L_BK_VE_ENC(0x5A), 0x3E},// ttvbi_st2
{H_BK_VE_ENC(0x5A), 0x01},
{L_BK_VE_ENC(0x5B), 0x4F},// ttvbi_end2
{H_BK_VE_ENC(0x5B), 0x01},
{L_BK_VE_ENC(0x5E), 0xDA},// vps_phs_step[15:0]
{H_BK_VE_ENC(0x5E), 0x4B},
{L_BK_VE_ENC(0x5F), 0x68},// vps_phs_step[31:16]
{H_BK_VE_ENC(0x5F), 0x2F},
{L_BK_VE_ENC(0x60), 0xDA},// wws_phs_step[15:0]
{H_BK_VE_ENC(0x60), 0x4B},
{L_BK_VE_ENC(0x61), 0x68},// wws_phs_step[31:16]
{H_BK_VE_ENC(0x61), 0x2F},
{L_BK_VE_ENC(0x62), 0x71},// tt_phs_step[15:0]
{H_BK_VE_ENC(0x62), 0x1C},
{L_BK_VE_ENC(0x63), 0xC7},// tt_phs_step[31:16]
{H_BK_VE_ENC(0x63), 0x41},
{L_BK_VE_ENC(0x65), 0x53},// vps_st
{H_BK_VE_ENC(0x65), 0x01},
{L_BK_VE_ENC(0x66), 0x30},// wws_st
{H_BK_VE_ENC(0x66), 0x01},
{L_BK_VE_ENC(0x67), 0x15},// tt_st
{H_BK_VE_ENC(0x67), 0x01},
{L_BK_VE_ENC(0x69), 0x90},// vps_lvl
{H_BK_VE_ENC(0x69), 0x01},
{L_BK_VE_ENC(0x6A), 0x90},// wws_lvl
{H_BK_VE_ENC(0x6A), 0x01},
{L_BK_VE_ENC(0x6B), 0x90},// tt_lvl
{H_BK_VE_ENC(0x6B), 0x01},
{L_BK_VE_ENC(0x3C), 0xFF},// tt_bitmap[15:0]
{H_BK_VE_ENC(0x3C), 0x00},
{L_BK_VE_ENC(0x3D), 0xFF},// tt_bitmap[31:16]
{H_BK_VE_ENC(0x3D), 0x00},
{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_CCIROUT_NTSC_TBL[] =
{
{L_BK_VE_SRC(0x47), 0x0D},// frame line number
{H_BK_VE_SRC(0x47), 0x02},
{L_BK_VE_SRC(0x48), 0x01},// F0 blank star
{H_BK_VE_SRC(0x48), 0x00},
{L_BK_VE_SRC(0x49), 0x17},// F0 blank end
{H_BK_VE_SRC(0x49), 0x00},
{L_BK_VE_SRC(0x4A), 0x07},// F1 blank start
{H_BK_VE_SRC(0x4A), 0x01},
{L_BK_VE_SRC(0x4B), 0x1E},// F1 blank end
{H_BK_VE_SRC(0x4B), 0x01},
{L_BK_VE_SRC(0x4C), 0x04},// F0 start
{H_BK_VE_SRC(0x4C), 0x00},
{L_BK_VE_SRC(0x4D), 0x0A},// F0 end
{H_BK_VE_SRC(0x4D), 0x01},
{L_BK_VE_SRC(0x4E), 0x01},// F0 V start
{H_BK_VE_SRC(0x4E), 0x00},
{L_BK_VE_SRC(0x4F), 0x14},// F0 V end
{H_BK_VE_SRC(0x4F), 0x00},
{L_BK_VE_SRC(0x50), 0x08},// F1 V start
{H_BK_VE_SRC(0x50), 0x01},
{L_BK_VE_SRC(0x51), 0x1B},// F1 V end
{H_BK_VE_SRC(0x51), 0x01},
{_END_OF_TBL_, 0x00},
};
code MS_REG_TYPE tVE_CCIROUT_PAL_TBL[] =
{
{L_BK_VE_SRC(0x47), 0x71},// frame line number
{H_BK_VE_SRC(0x47), 0x02},
{L_BK_VE_SRC(0x48), 0x01},// F0 blank star
{H_BK_VE_SRC(0x48), 0x00},
{L_BK_VE_SRC(0x49), 0x19},// F0 blank end
{H_BK_VE_SRC(0x49), 0x00},
{L_BK_VE_SRC(0x4A), 0x39},// F1 blank start
{H_BK_VE_SRC(0x4A), 0x01},
{L_BK_VE_SRC(0x4B), 0x52},// F1 blank end
{H_BK_VE_SRC(0x4B), 0x01},
{L_BK_VE_SRC(0x4C), 0x02},// F0 start
{H_BK_VE_SRC(0x4C), 0x00},
{L_BK_VE_SRC(0x4D), 0x3A},// F0 end
{H_BK_VE_SRC(0x4D), 0x01},
{L_BK_VE_SRC(0x4E), 0x07},// F0 V start
{H_BK_VE_SRC(0x4E), 0x01},
{L_BK_VE_SRC(0x4F), 0x18},// F0 V end
{H_BK_VE_SRC(0x4F), 0x00},
{L_BK_VE_SRC(0x50), 0x38},// F1 V start
{H_BK_VE_SRC(0x50), 0x01},
{L_BK_VE_SRC(0x51), 0x51},// F1 V end
{H_BK_VE_SRC(0x51), 0x01},
{_END_OF_TBL_, 0x00},
};
MS_VE_OUT_VIDEOSYS code VE_OUT_VIDEOSTD_TBL[MS_VE_VIDEOSYS_NUM] =
{ // Reg Tbl Coef_TBL VBI TBL vtotal_525, bPALSwitch, bPALOut
/*NSTC */ {tVE_ENCODER_NTSC_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0},
/*NSTC_443*/ {tVE_ENCODER_NTSC_443_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0},
/*NSTC_J*/ {tVE_ENCODER_NTSC_J_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0},
/*PAL_M*/ {tVE_ENCODER_PAL_M_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 0, 1, 1},
/*PAL_N*/ {tVE_ENCODER_PAL_N_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1},
/*PAL_NC*/ {tVE_ENCODER_PAL_NC_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1},
/*PAL_B*/ {tVE_ENCODER_PAL_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1},
};
MS_VE_OUT_DEST code VE_OUT_MATCH_TBL[MS_VE_DEST_NUM][MS_VE_DEST_NUM] =
{
// None SCART CVBS SVIDEO YPbPr
/*None */ {{1, VE_OUT_CVBS_YCC}, {1, VE_OUT_CVBS_RGB}, {1, VE_OUT_CVBS_YCC}, {1, VE_OUT_CVBS_YCC}, {1, VE_OUT_CVBS_YCbCr},},
/*SCART */ {{1, VE_OUT_CVBS_RGB}, {0, VE_OUT_NONE}, {0, VE_OUT_NONE}, {0, VE_OUT_NONE}, {0, VE_OUT_CVBS_YCC}, },
/*CVBS */ {{1, VE_OUT_CVBS_YCC}, {0, VE_OUT_NONE}, {0, VE_OUT_NONE}, {1, VE_OUT_CVBS_YCC}, {1, VE_OUT_CVBS_YCbCr},},
/*SVIDEO */ {{1, VE_OUT_CVBS_YCC}, {0, VE_OUT_NONE}, {1, VE_OUT_CVBS_YCC}, {0, VE_OUT_NONE}, {0, VE_OUT_CVBS_YCC}, },
/*YPbPr */ {{1, VE_OUT_CVBS_YCbCr},{0, VE_OUT_NONE}, {1, VE_OUT_CVBS_YCbCr}, {0, VE_OUT_NONE}, {0, VE_OUT_CVBS_YCC}, },
};
MS_VIDEO_CAPTUREWINTABLE_TYPE code VideoCapWinTbl [] =
{
//lachesis_070307 temporary for demo.
//{0x45, 0x0A, MSVD_HACTIVE_NTSC, 480, 58, 29}, // NSTC
{0x45, 0x0A, 764, 480, 46, 28}, // NSTC
{0x6C, 0x12, 720, 576, 40, 30}, // PAL
{0x62, 0x12, 720, 576, 50, 30}, // SECAM
{0x62, 0x09, 720, 480, 50, 30}, // NTSC-443/PAL-60
{0x41, 0x09, 720, 480, 50, 30}, // PAL-M
{0x41, 0x12, 720, 576, 50, 30}, // PAL-Nc
};
void MsWriteVEMask(U16 u16Addr, U8 u8Value, U8 u8Mask)
{
U8 u8Data;
u8Data = VE_REG(u16Addr) & (~u8Mask);
VE_REG(u16Addr) = u8Data | (u8Value & u8Mask);
}
void MsWriteVEReg(U16 u16addr, U16 u16Data)
{
//VE_REG(u16addr) = u16Data;
MDrv_Write2Byte(u16addr, u16Data);
}
void MsWriteVE4Byte(U16 u16addr, U32 u32Data)
{
VE_REG(u16addr) = u32Data & 0x000000FF;
VE_REG(u16addr+1) = (u32Data & 0x0000FF00) >> 8;
VE_REG(u16addr+2) = (u32Data & 0x00FF0000) >> 16;
VE_REG(u16addr+3) = (u32Data & 0xFF000000) >> 24;
}
void MsWriteVEBit(U16 u16addr, BOOLEAN bval, U16 bitpos)
{
U16 u16RegVal;
u16RegVal = VE_REG(u16addr);
if(bval)
{
u16RegVal |= bitpos;
}
else
{
u16RegVal &= ~bitpos;
}
VE_REG(u16addr) = u16RegVal;
}
void MsWriteVERegTbl(pRegUnitType pTable)
{
U16 u16RegVal;
S32 s32addr;
while(1)
{
s32addr = pTable->s16Idx;
if(s32addr == _END_OF_TBL_)
break;
if(s32addr == _REG_BASE_TBL)
g_u32VERregBase = (pTable->u16Val << 2);
else
{
s32addr += g_u32VERregBase;
if(pTable->s16Idx & BK_LOW_BIT)
{
u16RegVal = VE_REG(s32addr & BK_LH_MASK) & 0xFF00;
u16RegVal |= pTable->u16Val & 0x00FF;
VE_REG(s32addr & BK_LH_MASK) = u16RegVal;
}
else if(pTable->s16Idx & BK_HIGH_BIT)
{
u16RegVal = VE_REG(s32addr & BK_LH_MASK) & 0x00FF;
u16RegVal |= pTable->u16Val & 0xFF00;
VE_REG(s32addr & BK_LH_MASK) = u16RegVal;
}
else
{
VE_REG(s32addr) = pTable->u16Val;
}
}
pTable++;
}
}
void MDrv_WriteVERegTbl ( MS_REG_TYPE *pRegTable )
{
U16 u16Index; // register index
U16 u16Dummy;
u16Dummy = 65535;
while (1)
{
u16Index = pRegTable->u16Index; // get register index
if (u16Index == _END_OF_TBL_) // check end of table
break;
XBYTE[u16Index] = pRegTable->u8Value; // write register
pRegTable++; // next
if ( (u16Dummy--) == 0 )
break;
} // while
}
//------------------------------------------------------------------------------
/// set frame rate convert
///
/// @param none
/// @return none
//------------------------------------------------------------------------------
void _MDrv_VE_Set_FRC(void)
{
U32 u32FullNum, u32EmptyNum;
U32 u32FrameSize;
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