drvtvencoder.c

mstar 776 开发的车载dvd

////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (!!∮MStar Confidential Information!!L) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
////////////////////////////////////////////////////////////////////////////////
#include "board.h"
#include <string.h>
#include "drvTVEncoder.h"
#include "drvScaler.h"
#include "drvPower.h"
#include "drvAnalog_inline.h"
#include "drvtimer.h"
#include "drvMode.h"


#if ( ENABLE_VE )
// Need to Refine
#define  VE_MIU_BASE    VE_FRAMEBUFFER_ADR/8  //MVD_FRAMEBUFFER_ADR/8 //0x0

#define VE_NTSC_FRAME_SIZE  ((U32)(720ul * 480ul)>>2) // 720*480*16bits/64bits
#define VE_PAL_FRAME_SIZE   ((U32)(720ul * 576ul)>>2) // 720*576*16bits/64bits
#define VE_FRC_TOLERANT     10
#define VE_V_SCALE_DOWN_RATIO(IN, OUT)  ((U32)(OUT-3) * 2048ul / (U32)(IN-3))
#define VE_H_SCALE_DOWN_RATIO(IN, OUT)  ((U32)(OUT) * 2048ul / (U32)(IN))

// Need to Refine
 #define REG_VE_BASE         (0x0000) //(0x7E00)
 //#define VE_REG(addr)        (*(volatile U16 *)(REG_VE_BASE + (addr)))
 #define VE_REG(addr)    (XBYTE[REG_VE_BASE + (addr)])

/* VE */
#define L_BK_VE_ENC(x)      BK_REG_L(REG_BASE_VE_ENCODER, x)
#define H_BK_VE_ENC(x)      BK_REG_H(REG_BASE_VE_ENCODER, x)
#define L_BK_VE_SRC(x)      BK_REG_L(REG_BASE_VE_SOURCE, x)
#define H_BK_VE_SRC(x)      BK_REG_H(REG_BASE_VE_SOURCE, x)

#define MSG_DRV_VE(x)  //x


extern MS_VIDEO_CAPTUREWINTABLE_TYPE code ExtVDVideoCapture[];
extern MS_VIDEO_CAPTUREWINTABLE_TYPE code VideoCaptureWinTbl [];

 U32 g_u32VERregBase = 0;

//===The table below modified to match S2 setting===//

code MS_REG_TYPE  tVE_ENCODER_NTSC_TBL[] =
{
//video encoder
    {L_BK_VE_ENC(0x00), 0x01},// hsync start
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x94},// burst start
    {H_BK_VE_ENC(0x01), 0xD7},// burst end
    {L_BK_VE_ENC(0x02), 0x28},
    {H_BK_VE_ENC(0x02), 0x00},
//    {L_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x03), 0x02},// for VM700
    {H_BK_VE_ENC(0x03), 0x00},
//    {L_BK_VE_ENC(0x04), 0x4C},// contrast
//    {H_BK_VE_ENC(0x04), 0x77},// brightness
    {L_BK_VE_ENC(0x04), 0x48},// contrast // for VM700
    {H_BK_VE_ENC(0x04), 0x7A},// brightness // for VM700
    {L_BK_VE_ENC(0x06), 0x00},
    {H_BK_VE_ENC(0x06), 0x00},
    {L_BK_VE_ENC(0x09), 0xB4},// h total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0x1F},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x7C},
    {L_BK_VE_ENC(0x0C), 0xF0},
    {H_BK_VE_ENC(0x0C), 0x21},
    {L_BK_VE_ENC(0x0D), 0xD0},
    {H_BK_VE_ENC(0x0D), 0x00},
    {L_BK_VE_ENC(0x0E), 0x00},
    {H_BK_VE_ENC(0x0E), 0x00},
    {L_BK_VE_ENC(0x25), 0x00},// av st
    {H_BK_VE_ENC(0x25), 0x01},
    {L_BK_VE_ENC(0x26), 0x8D},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x2A},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xF0},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x38},
    {L_BK_VE_ENC(0x29), 0x13},// burst amp & step
    {H_BK_VE_ENC(0x29), 0x70},
    //{L_BK_VE_ENC(0x2A), 0x41},
    //{H_BK_VE_ENC(0x2A), 0x5B},
    {L_BK_VE_ENC(0x2A), 0x4C},// for VM700
    {H_BK_VE_ENC(0x2A), 0x66},//for VM700
    {L_BK_VE_ENC(0x2E), 0x00},
    {H_BK_VE_ENC(0x2E), 0x00},

    {L_BK_VE_ENC(0x78), 0x00},// disable MV

//video source
    {L_BK_VE_SRC(0x42), 0xE0},// Frame line num
    {H_BK_VE_SRC(0x42), 0x01},
    {L_BK_VE_SRC(0x45), 0xC0},// Field Size
    {H_BK_VE_SRC(0x45), 0xA8},

    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_NTSC_443_TBL[] =
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x8E},// burst st
    {H_BK_VE_ENC(0x01), 0xD1},// burst end
    {L_BK_VE_ENC(0x02), 0x00},
    {H_BK_VE_ENC(0x02), 0x00},
    {L_BK_VE_ENC(0x03), 0x00},
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x40},// contrast
    {H_BK_VE_ENC(0x04), 0x80},// brightness
    {L_BK_VE_ENC(0x09), 0xB4},// h total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0x1F},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x7C},
    {L_BK_VE_ENC(0x0C), 0xF0},
    {H_BK_VE_ENC(0x0C), 0x12},
    {L_BK_VE_ENC(0x0D), 0xD0},
    {H_BK_VE_ENC(0x0D), 0x00},
    {L_BK_VE_ENC(0x0E), 0x00},
    {H_BK_VE_ENC(0x0E), 0x00},
    {L_BK_VE_ENC(0x25), 0xFF},// av st
    {H_BK_VE_ENC(0x25), 0x00},
    {L_BK_VE_ENC(0x26), 0x8D},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x2A},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xF0},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x38},
    {L_BK_VE_ENC(0x29), 0x0E},// burst amp & step
    {H_BK_VE_ENC(0x29), 0x70},

    {L_BK_VE_SRC(0x42), 0xE0},// Frame line num
    {H_BK_VE_SRC(0x42), 0x01},
    {L_BK_VE_SRC(0x45), 0x60},// Field Size
    {H_BK_VE_SRC(0x45), 0x54},
    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_NTSC_J_TBL[] =
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x8E},// burst st
    {H_BK_VE_ENC(0x01), 0xD1},// burst end
    {L_BK_VE_ENC(0x02), 0x00},
    {H_BK_VE_ENC(0x02), 0x00},
    {L_BK_VE_ENC(0x03), 0x00},
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x40},// contrast
    {H_BK_VE_ENC(0x04), 0x80},// brightness
    {L_BK_VE_ENC(0x09), 0xB4},// H total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0x1F},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x7C},
    {L_BK_VE_ENC(0x0C), 0xF0},
    {H_BK_VE_ENC(0x0C), 0x12},
    {L_BK_VE_ENC(0x0D), 0xD0},// lower stage fraction
    {H_BK_VE_ENC(0x0D), 0x00},
    {L_BK_VE_ENC(0x0E), 0x00},// 625 stage fraction
    {H_BK_VE_ENC(0x0E), 0x00},
    {L_BK_VE_ENC(0x25), 0xFF},// av st
    {H_BK_VE_ENC(0x25), 0x00},
    {L_BK_VE_ENC(0x26), 0x8D},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x00},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xF0},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x38},
    {L_BK_VE_ENC(0x29), 0x0E},// burst amp & burst step
    {H_BK_VE_ENC(0x29), 0x70},

    {L_BK_VE_SRC(0x42), 0xE0},// Frame line number
    {H_BK_VE_SRC(0x42), 0x01},
    {L_BK_VE_SRC(0x45), 0x60},// Field Size
    {H_BK_VE_SRC(0x45), 0x54},
    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_PAL_M_TBL[] =
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x9B},// burst st
    {H_BK_VE_ENC(0x01), 0xDE},// burst end
    {L_BK_VE_ENC(0x02), 0x88},
    {H_BK_VE_ENC(0x02), 0x00},
    {L_BK_VE_ENC(0x03), 0x0A},
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x40},// contrast
    {H_BK_VE_ENC(0x04), 0x80},// brightness
    {L_BK_VE_ENC(0x09), 0xB4},// H total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0xE3},// burst phase step
    {H_BK_VE_ENC(0x0B), 0xEF},
    {L_BK_VE_ENC(0x0C), 0xE6},
    {H_BK_VE_ENC(0x0C), 0x21},
    {L_BK_VE_ENC(0x0D), 0x90},// lower stage fraction
    {H_BK_VE_ENC(0x0D), 0x09},
    {L_BK_VE_ENC(0x0E), 0x00},// 625 stage fraction
    {H_BK_VE_ENC(0x0E), 0x00},
    {L_BK_VE_ENC(0x25), 0xFA},// av st
    {H_BK_VE_ENC(0x25), 0x00},
    {L_BK_VE_ENC(0x26), 0x8C},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x2A},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xF0},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x38},
    {L_BK_VE_ENC(0x29), 0x0E},// burst amp & burst step
    {H_BK_VE_ENC(0x29), 0x75},

    {L_BK_VE_SRC(0x42), 0x40},// Frame line number
    {H_BK_VE_SRC(0x42), 0x02},
    {L_BK_VE_SRC(0x45), 0x40},// Field Size
    {H_BK_VE_SRC(0x45), 0x65},
    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_PAL_N_TBL[] =
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x86},// hsync end
    {L_BK_VE_ENC(0x01), 0x97},// burst st
    {H_BK_VE_ENC(0x01), 0xE1},// burst end
    {L_BK_VE_ENC(0x02), 0x88},
    {H_BK_VE_ENC(0x02), 0x00},
    {L_BK_VE_ENC(0x03), 0x0A},
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x40},// contrast
    {H_BK_VE_ENC(0x04), 0x80},// brightness
    {L_BK_VE_ENC(0x09), 0xC0},// H total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0xBC},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x8A},
    {L_BK_VE_ENC(0x0C), 0x09},
    {H_BK_VE_ENC(0x0C), 0x2A},
    {L_BK_VE_ENC(0x0D), 0x2E},// lower stage fraction
    {H_BK_VE_ENC(0x0D), 0x05},
    {L_BK_VE_ENC(0x0E), 0xB2},// 625 stage fraction
    {H_BK_VE_ENC(0x0E), 0x01},
    {L_BK_VE_ENC(0x25), 0xFE},// av st
    {H_BK_VE_ENC(0x25), 0x00},
    {L_BK_VE_ENC(0x26), 0x96},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x2A},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xF0},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x28},
    {L_BK_VE_ENC(0x29), 0x0F},// burst amp & burst step
    {H_BK_VE_ENC(0x29), 0x75},

    {L_BK_VE_SRC(0x42), 0x40},// Frame line number
    {H_BK_VE_SRC(0x42), 0x02},
    {L_BK_VE_SRC(0x45), 0x40},// Field Size
    {H_BK_VE_SRC(0x45), 0x65},
    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_PAL_NC_TBL[] =
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x97},// burst st
    {H_BK_VE_ENC(0x01), 0xD3},// burst end
    {L_BK_VE_ENC(0x02), 0x88},
    {H_BK_VE_ENC(0x02), 0x00},
    {L_BK_VE_ENC(0x03), 0x0A},
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x40},// contrast
    {H_BK_VE_ENC(0x04), 0x80},// brightness
    {L_BK_VE_ENC(0x09), 0xC0},// H total
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0x46},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x94},
    {L_BK_VE_ENC(0x0C), 0xF6},
    {H_BK_VE_ENC(0x0C), 0x21},
    {L_BK_VE_ENC(0x0D), 0x2E},// lower stage fraction
    {H_BK_VE_ENC(0x0D), 0x0C},
    {L_BK_VE_ENC(0x0E), 0xB2},// 625 stage fraction
    {H_BK_VE_ENC(0x0E), 0x01},
    {L_BK_VE_ENC(0x25), 0x17},// av st
    {H_BK_VE_ENC(0x25), 0x01},
    {L_BK_VE_ENC(0x26), 0x96},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x00},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xFC},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x28},
    {L_BK_VE_ENC(0x29), 0x0F},// burst amp & burst step
    {H_BK_VE_ENC(0x29), 0x75},

    {L_BK_VE_SRC(0x42), 0x40},// Frame line number
    {H_BK_VE_SRC(0x42), 0x02},
    {L_BK_VE_SRC(0x45), 0x40},// Field Size
    {H_BK_VE_SRC(0x45), 0x65},
    {_END_OF_TBL_, 0x00},
};

code MS_REG_TYPE  tVE_ENCODER_PAL_TBL[] =   //for DTV/ATV
{
    {L_BK_VE_ENC(0x00), 0x01},// hsync st
    {H_BK_VE_ENC(0x00), 0x7F},// hsync end
    {L_BK_VE_ENC(0x01), 0x9d},// burst st
    {H_BK_VE_ENC(0x01), 0xD9},// burst end
    {L_BK_VE_ENC(0x02), 0x28},
    {H_BK_VE_ENC(0x02), 0x00},
//    {L_BK_VE_ENC(0x03), 0x08},
    {L_BK_VE_ENC(0x03), 0x0A},// for VM700
    {H_BK_VE_ENC(0x03), 0x00},
    {L_BK_VE_ENC(0x04), 0x50},// contrast
    {H_BK_VE_ENC(0x04), 0x76},// brightness
    {L_BK_VE_ENC(0x06), 0x01},// H total
    {H_BK_VE_ENC(0x06), 0x00},
    {L_BK_VE_ENC(0x09), 0xC0},
    {H_BK_VE_ENC(0x09), 0x06},
    {L_BK_VE_ENC(0x0B), 0xCB},// burst phase step
    {H_BK_VE_ENC(0x0B), 0x8A},
    {L_BK_VE_ENC(0x0C), 0x09},
    {H_BK_VE_ENC(0x0C), 0x2A},
    {L_BK_VE_ENC(0x0D), 0x2E},// lower stage fraction
    {H_BK_VE_ENC(0x0D), 0x05},
    {L_BK_VE_ENC(0x0E), 0xB2},// 625 stage fraction
    {H_BK_VE_ENC(0x0E), 0x01},
    {L_BK_VE_ENC(0x25), 0x17},// av st
    {H_BK_VE_ENC(0x25), 0x01},
    {L_BK_VE_ENC(0x26), 0x96},// av end
    {H_BK_VE_ENC(0x26), 0x06},
    {L_BK_VE_ENC(0x27), 0x00},// sync tip level & pad level
    {H_BK_VE_ENC(0x27), 0x10},
    {L_BK_VE_ENC(0x28), 0xFC},// sync step & blank level
    {H_BK_VE_ENC(0x28), 0x28},
    {L_BK_VE_ENC(0x29), 0x14},// burst amp & burst step
    {H_BK_VE_ENC(0x29), 0x75},
//    {L_BK_VE_ENC(0x2A), 0x44},
//    {H_BK_VE_ENC(0x2A), 0x60},
    {L_BK_VE_ENC(0x2A), 0x54},
    {H_BK_VE_ENC(0x2A), 0x70},
    //{L_BK_VE_ENC(0x2E), 0x88}, //modify for digital TTX
    //{H_BK_VE_ENC(0x2E), 0x00},

    {L_BK_VE_ENC(0x78), 0x00},// disable MV

    {L_BK_VE_SRC(0x42), 0x40},// Frame line number
    {H_BK_VE_SRC(0x42), 0x02},
    {L_BK_VE_SRC(0x45), 0x80},// Field Size
    {H_BK_VE_SRC(0x45), 0xCA},