drvsys.c

mstar 776 开发的车载dvd

                         (VDMCU_CLOCK_INVERT ? VDMCU_CLK_INVERT:VDMCU_CLK_NONINVERT)|
                         /*((VDMCU_CLOCK_SEL == VDMCU_CLOCK_54MHZ) ? VDMCU_CLK_54MHZ:
                          (VDMCU_CLOCK_SEL == VDMCU_CLOCK_61MHZ) ? VDMCU_CLK_61MHZ:
                          (VDMCU_CLOCK_SEL == VDMCU_CLOCK_30MHZ) ? VDMCU_CLK_30MHZ:
                          (VDMCU_CLOCK_SEL == VDMCU_CLOCK_108MHZ) ? VDMCU_CLK_108MHZ:VDMCU_CLK_54MHZ)|*/
                         (VD200_CLOCK_ENABLE ? VD200_CLK_ENABLE:VD200_CLK_DISABLE)|
                         (VD200_CLOCK_INVERT ? VD200_CLK_INVERT:VD200_CLK_NONINVERT)|
                         ((VD200_CLOCK_SEL == VD200_CLOCK_216MHZ) ? VD200_CLK_216MHZ:
                          (VD200_CLOCK_SEL == VD200_CLOCK_0MHZ0) ? VD200_CLK_0MHZ0:
                          (VD200_CLOCK_SEL == VD200_CLOCK_0MHZ1) ? VD200_CLK_0MHZ1:
                          (VD200_CLOCK_SEL == VD200_CLOCK_XTAL) ? VD200_CLK_XTAL:VD200_CLK_216MHZ);


    XBYTE[REG_CKG_FICLK] = (FICLKF2_CLOCK_ENABLE ? FICLKF2_CLK_ENABLE:FICLKF2_CLK_DISABLE)|
                           (FICLKF2_CLOCK_INVERT ? FICLKF2_CLK_INVERT:FICLKF2_CLK_NONINVERT)|
                           ((FICLKF2_CLOCK_SEL == FICLKF2_CLOCK_IDCLK2) ? FICLKF2_CLK_IDCLK2:
                            (FICLKF2_CLOCK_SEL == FICLKF2_CLOCK_FCLK) ? FICLKF2_CLK_FCLK:
                            (FICLKF2_CLOCK_SEL == FICLKF2_CLOCK_IDCLK1) ? FICLKF2_CLK_IDCLK1:
                            (FICLKF2_CLOCK_SEL == FICLKF2_CLOCK_XTAL) ? FICLKF2_CLK_XTAL:FICLKF2_CLK_IDCLK2)|

                            (FICLKF1_CLOCK_ENABLE ? FICLKF1_CLK_ENABLE:FICLKF1_CLK_DISABLE)|
                           (FICLKF1_CLOCK_INVERT ? FICLKF1_CLK_INVERT:FICLKF1_CLK_NONINVERT)|
                           ((FICLKF1_CLOCK_SEL == FICLKF1_CLOCK_IDCLK2) ? FICLKF1_CLK_IDCLK2:
                            (FICLKF1_CLOCK_SEL == FICLKF1_CLOCK_FCLK) ? FICLKF1_CLK_FCLK:
                            (FICLKF1_CLOCK_SEL == FICLKF1_CLOCK_IDCLK1) ? FICLKF1_CLK_IDCLK1:
                            (FICLKF1_CLOCK_SEL == FICLKF1_CLOCK_XTAL) ? FICLKF1_CLK_XTAL:FICLKF1_CLK_IDCLK2);


    XBYTE[REG_CKG_SDRDAC] = (DAC_CLOCK_ENABLE ? DAC_CLK_ENABLE:DAC_CLK_DISABLE)|
                            (DAC_CLOCK_INVERT ? DAC_CLK_INVERT:DAC_CLK_NONINVERT)|
                            ((DAC_CLOCK_SEL == DAC_CLOCK_ODCLK) ? DAC_CLK_ODCLK:
                             (DAC_CLOCK_SEL == DAC_CLOCK_0) ? DAC_CLK_0:
                             (DAC_CLOCK_SEL == DAC_CLOCK_VD) ? DAC_CLK_VD:
                             (DAC_CLOCK_SEL == DAC_CLOCK_XTAL) ? DAC_CLK_XTAL:DAC_CLK_ODCLK);

    XBYTE[REG_CKG_FCLK] = (FCLK_CLOCK_ENABLE ? FCLK_CLK_ENABLE:FCLK_CLK_DISABLE)|
                          (FCLK_CLOCK_INVERT ? FCLK_CLK_INVERT:FCLK_CLK_NONINVERT)|
                          ((FCLK_CLOCK_SEL == FCLK_CLOCK_MPLL) ? FCLK_CLK_MPLL:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_MIU) ? FCLK_CLK_MIU:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_ODCLK) ? FCLK_CLK_ODCLK:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_IDCLK1) ? FCLK_CLK_IDCLK1:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_IDCLK2) ? FCLK_CLK_IDCLK2:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_0_1) ? FCLK_CLK_0_1:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_0_2) ? FCLK_CLK_0_2:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_XTAL_0) ? FCLK_CLK_XTAL_0:
                           (FCLK_CLOCK_SEL == FCLK_CLOCK_XTAL_1) ? FCLK_CLK_XTAL_1:FCLK_CLK_MPLL);

    XBYTE[REG_CKG_FMCLK] = (FMCLK_CLOCK_ENABLE ? FMCLK_CLK_ENABLE:FMCLK_CLK_DISABLE)|
                           (FMCLK_CLOCK_INVERT ? FMCLK_CLK_INVERT:FMCLK_CLK_NONINVERT)|
                           ((FMCLK_CLOCK_SEL == FMCLK_CLOCK_MIU) ? FMCLK_CLK_MIU:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_MPLL) ? FMCLK_CLK_MPLL:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_ODCLK) ? FMCLK_CLK_ODCLK:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_IDCLK1) ? FMCLK_CLK_IDCLK1:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_IDCLK2) ? FMCLK_CLK_IDCLK2:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_0_1) ? FMCLK_CLK_0_1:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_0_2) ? FMCLK_CLK_0_2:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_0_3) ? FMCLK_CLK_0_3:
                            (FMCLK_CLOCK_SEL == FMCLK_CLOCK_DFT) ? FMCLK_CLK_DFT:FMCLK_CLK_MIU);

    XBYTE[REG_CKG_ODCLK] = (ODCLK_CLOCK_ENABLE ? ODCLK_CLK_ENABLE:ODCLK_CLK_DISABLE)|
                           (ODCLK_CLOCK_INVERT ? ODCLK_CLK_INVERT:ODCLK_CLK_NONINVERT)|
                           ((ODCLK_CLOCK_SEL == ODCLK_CLOCK_ADC) ? ODCLK_CLK_ADC:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_VD) ? ODCLK_CLK_VD:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_1) ? ODCLK_CLK_1:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_EX_DI) ? ODCLK_CLK_EX_DI:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_XTAL_0) ? ODCLK_CLK_XTAL_0:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_LPLL) ? ODCLK_CLK_LPLL:
                            (ODCLK_CLOCK_SEL == ODCLK_CLOCK_XTAL_1) ? ODCLK_CLK_XTAL_1:ODCLK_CLK_ADC);

    XBYTE[REG_CKG_IDCLK1] = (IDCLK1_CLOCK_ENABLE ? IDCLK1_CLK_ENABLE:IDCLK1_CLK_DISABLE)|
                            (IDCLK1_CLOCK_INVERT ? IDCLK1_CLK_INVERT:IDCLK1_CLK_NONINVERT)|
                            ((IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_ADC) ? IDCLK1_CLK_ADC:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_VD) ? IDCLK1_CLK_VD:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_DC0) ? IDCLK1_CLK_DC0:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_VD20) ? IDCLK1_CLK_VD20:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_EX_DI) ? IDCLK1_CLK_EX_DI:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_VDADC) ? IDCLK1_CLK_VDADC:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_0) ? IDCLK1_CLK_0:
                             (IDCLK1_CLOCK_SEL == IDCLK1_CLOCK_XTAL) ? IDCLK1_CLK_XTAL:IDCLK1_CLK_ADC);


    XBYTE[REG_CKG_IDCLK2] = (IDCLK2_CLOCK_ENABLE ? IDCLK2_CLK_ENABLE:IDCLK2_CLK_DISABLE)|
                            (IDCLK2_CLOCK_INVERT ? IDCLK2_CLK_INVERT:IDCLK2_CLK_NONINVERT)|
                            ((IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_ADC) ? IDCLK2_CLK_ADC:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_VD) ? IDCLK2_CLK_VD:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_DC0) ? IDCLK2_CLK_DC0:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_VD20) ? IDCLK2_CLK_VD20:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_EX_DI) ? IDCLK2_CLK_EX_DI:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_VDADC) ? IDCLK2_CLK_VDADC:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_0) ? IDCLK2_CLK_0:
                             (IDCLK2_CLOCK_SEL == IDCLK2_CLOCK_XTAL) ? IDCLK2_CLK_XTAL:IDCLK2_CLK_ADC);
}

/******************************************************************************/
/******************************************************************************/
#if BOOTUP_MIU_BIST
static void MDrv_MIU_BIST( void )
{
    MDrv_Write2Byte( REG_MIU_TEST_BASE, 0x0000 );     // in 256 words (2kbytes)

    // test all 32MB memory
    MDrv_Write3Byte( REG_MIU_TEST_LENGTH, (MEMOEY_SIZE / 8)); // in word

    MDrv_Write2Byte( REG_MIU_TEST_DATA, 0xA55A );

    // enable test, order (high byte then low byte) is important
    MDrv_WriteByte( REG_MIU_TEST_MODE + 1, 0x00 );
    MDrv_WriteByte( REG_MIU_TEST_MODE, 0x03 );        // pattern from data

    // don't use timeout, let watchdog to handle it

    DRVSYS(putchar( 'B' ));
    DRVSYS(putchar( 'I' ));
    DRVSYS(putchar( 'S' ));
    DRVSYS(putchar( 'T' ));
    DRVSYS(putchar( ':' ));

    while ( !MDrv_ReadRegBit( REG_MIU_TEST_MODE + 1, _BIT7 ) ) ;

    if ( MDrv_ReadRegBit( REG_MIU_TEST_MODE + 1, _BIT6 ) )
    {
        DRVSYS(putchar( 'N' ));
        DRVSYS(putchar( 'G' ));
    }
    else
    {
        DRVSYS(putchar( 'O' ));
        DRVSYS(putchar( 'K' ));
    }

    DRVSYS(putchar( '\r' ));
    DRVSYS(putchar( '\n' ));
}
#endif


#define UART_HK51_0	0x00
#define UART_HK51_1	0x01
#define UART_VD		0x02
#define UART_FIFO	0x05
#define UART_PAD_0	UART_HK51_0
#define UART_PAD_1	UART_HK51_1

#define MDrv_Moses_SetUartPad(DgMux1,DgMux0) MDrv_WriteByteMask(BK_CHIPTOP_55_L,(DgMux1<<5)|(DgMux0<<2),0xFC)

/******************************************************************************/
/// This function is called by startup.a51
/******************************************************************************/
void MDrv_Saturn2_SystemInitial( void  )
{
#if 1
    CKCON = 0x01;   // for XDATA access
    XBYTE[BK_PIU_MISC_20_H] = (XBYTE[BK_PIU_MISC_20_H] & 0xf0 )|0x09;   //legnth of CSZ on spi_flash

	MDrv_Moses_SetUartPad(UART_PAD_1,UART_PAD_0);

    MDrv_Sys_InitUartForXtalClk( '*' );

	// seven 070906_00
	MDrv_WriteRegBit(BK_MCU_0C_L,TRUE,_BIT3); // disable cache reset
	MDrv_WriteRegBit(BK_2B_50_L,FALSE,_BIT0); // disable cache pass mode
	// end

    //---------------------------------------------
    // Configure pin functions
    //---------------------------------------------
    // clear all test register setting,

    XBYTE[REG_MUX_CONFIG_2] &= ~ TEST_OUT_MODE;

    MDrv_Sys_InitialPll();

    Mst_GPIO_Initial();

    // Power down DACA, DACR, DACG, DACB
    XBYTE[0x3206] |= 0x0F;

    if (MDrv_Sys_IsCodeInSPI())
    {
        //DRVSYS(puts("Code Run in SPI!"));
        puts("Code Run in SPI!");

        // Setting MIU Group Request Mask
        XBYTE[0x1246] = 0xFE;
        XBYTE[0x1247] = 0xFF;

        MDrv_Sys_InitialMiu();

        // Setting MIU Group Request Mask
        XBYTE[0x1246] = 0x00;
        XBYTE[0x1247] = 0x00;

        #if BOOTUP_MIU_BIST
        MDrv_MIU_BIST();
        #endif
    }

    XBYTE[XDMIU_REG_BASE + 4] &= ~0x04;   //xdata miu disable

    XBYTE[XDMIU_REG_BASE + 6] = (XDATA_DRAM_START_ADDR / 1024);
    XBYTE[XDMIU_REG_BASE + 7] = (XDATA_WIN1_START_ADDR / 1024);
    XBYTE[XDMIU_REG_BASE + 8] = LOWBYTE(XD_MAP_BASE_ADR / 65536);   // 64kbyte unit
    XBYTE[XDMIU_REG_BASE + 9] = HIGHBYTE(XD_MAP_BASE_ADR / 65536);

    XBYTE[XDMIU_REG_BASE + 10] = (XDATA_WIN1_START_ADDR / 1024);
    XBYTE[XDMIU_REG_BASE + 11] = ((XDATA_WIN1_START_ADDR + XDATA_WIN1_SIZE) / 1024);
    XBYTE[XDMIU_REG_BASE + 12] = LOWBYTE((XD_MAP_BASE_ADR + XDATA_WIN1_SIZE) / 4096);  //4kbyte unit
    XBYTE[XDMIU_REG_BASE + 13] = HIGHBYTE((XD_MAP_BASE_ADR + XDATA_WIN1_SIZE) / 4096);

    XBYTE[XDMIU_REG_BASE + 4] |= 0x04;   //enable xdata miu

	// seven 070906_00
    // Setting SPI Clock
//    XBYTE[0x3c40]=0xff;
//    XBYTE[0x3c41]=( XBYTE[0x3c41] & 0xf0 ) | 0x0f;
//    XBYTE[0x3c41]|=0x80;
//    XBYTE[0x3c4c]=(XBYTE[0x3c4c] & 0xe3) | BIT4;
	// end

#if (ENABLE_POWER_GOOD_DETECT)
    XBYTE[0x12A3] |= 0x04;
    XBYTE[0x1E72] |= 0x40;
    XBYTE[0x1E72] |= 0x1F;
#endif

    if ((XBYTE[WDT_RST] & BIT0))
        DRVSYS(printf("WDT occured\r\n"));

    if (DOWNLOAD_RUN_SERVER)
    {
        MDrv_Sys_SetInterrupt( GLOBAL, DISABLE );
        DRVSYS(printf("Ready to receive FW code\r\n"));

        while (1)
        {
            _nop_();
            MDrv_Sys_ClearWatchDog();
        }
    }
    else
    {
        if (WATCH_DOG == ENABLE)
            MDrv_Sys_ClearWatchDog();
        else
            MDrv_Sys_DisableWatchDog();
    }
#endif
        MDrv_WriteRegBit( 0x2B03,0x00,_BIT7);

	// boost init
	MDrv_WriteByte(BK_34_5B_L,0x01);
	MDrv_WriteByte(BK_34_5E_L,0x00);
	MDrv_WriteByte(BK_34_5F_L,0x20);

	// Select IP1_2F_01
	MDrv_WriteByte(BK_IP1_16_45_H,0x80);

	// GPO gating
	MDrv_WriteRegBit(BK_TCON_4A_H,TRUE,BIT0);

}

/******************************************************************************/
//
//   128T +------+          +------+ 128T
//     |  |      |          |      |  |
//     +--+ 8051 |          | Aeon +--+
//        |      |          |      |
//        +--+---+          +---+--+
//       +---+----+        +----+---+
//       |        |        |        |
//   boot_aeon   sw_rst   sw_rst  boot_8051
//
// When boot from 8051
//      reboot:   use reg_reset_cpu0 with password
//      run aeon: set reg_sw_reset_cpu1 to 1
// When boot from Aeon
//      reboot:   use reg_reset_cpu1 with password
//      run 8051: set reg_sw_reset_cpu0 to 1
/******************************************************************************/

/******************************************************************************/
///Reset 8051 to reboot
/******************************************************************************/
void MDrv_Sys_Reboot( void )
{
    // write password to self reset (no memory except registers will be accessed)
    MDrv_Write2Byte( REG_RESET_CPU_8051, 0x029F );
    MDrv_Write2Byte( REG_RESET_CPU_8051, 0x829F ); // can't ignore second 0x9F

    while(1);
}