drvsys.c

mstar 776 开发的车载dvd

////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
///@file drvsys.h
///@brief System functions: Initialize, interrupt
///@author MStarSemi Inc.
///
///////////////////////////////////////////////////////////////////////////////

#define  _DRV_SYS_C_

#include "debug.h"
#include "mreg51.h"
#include "sysinfo.h"
#include "hwreg.h"
#include "drvuart.h"
#include "drvmiu.h"
#include "drvsys.h"
#include "Analog_Reg.h"
#include "drvGlobal.h"
#include "drvISR.h"
#include "drviic.h"
#include "drvscaler.h"
#include <intrins.h>
#include <stdio.h>
#include "DrvGpio.h"
#include "DrvCpu.h"

/******************************************************************************/
/*                     Local Defines                                          */
/******************************************************************************/

// set 1 to enable support for download image to dram and run from MSTV_Tool
#define DOWNLOAD_RUN_SERVER     0

#define ASSERT(expr)    __ASSERT(expr)

#define DRVSYS(x)       //x

/******************************************************************************/
/*                     Global Variables                                       */
/******************************************************************************/

// memory map for pre-built libraries

U32 u32XDataAddr = XD_MAP_BASE_ADR;
U32 u32XDataSize = XD_MAP_LEN;

U32 u32CodeAddr = CODE_MAP_BASE_ADR;
U32 u32CodeSize = CODE_MAP_LEN;

//----------------------------------------
// It'll be called by drvDLC.obj
U8 u8ChipVer _at_ REG_CHIP_VERSION;
#if ENABLE_DLC
U8 u8ChipRev = 1;// temp solution
#else
U8 u8ChipRev _at_ REG_CHIP_REVISION;
#endif

//----------------------------------------

static code MS_REG_INIT MiuSettingFixup[] =
{
    // setup MIU client priority
    // for bandwidth issue, must be refined later
    // kevin //_RV1(0x1206, 0xA0),     // refresh cycle period

    //_RV1(0x1252, 0xFF),
    _RV1(0x1253, 0xFF),     // group0 deadline, unit 64
    _RV1(0x1254, 0xFF),     // group0 mcu read request flow control counter
    _RV1(0x1255, 0xFF),     // group0 mcu write request flow control counter
    _RV1(0x1256, 0xFF),     // group0 tsp read request flow control counter
    _RV1(0x1257, 0xFF),     // group0 tsp write request flow control counter

    // soft reset
    _RV1(0x121E, 0x01),
    _RV1(0x121E, 0x00),

    // issue initial miu cycle
    _RV2(0x1200, 0x0001),

    _END_OF_TBL2_
};

/******************************************************************************/
static void MDrv_Sys_InitialMiu ( void )
{
    MDrv_MIU_InitialMiuToSDRAMX16();

    MDrv_WriteRegTbl(MiuSettingFixup);

    // wait for initial done flag
    while ( (XBYTE[0x1201] & 0x80) == 0 );
}

/******************************************************************************/
void MDrv_Sys_Set_ECC_DMA(U8 mode)
{
    if (mode == DISABLE)
    {
        XBYTE[ECC_MODE0] |= ECC_DMA_WR_BYPASS_EN +
                            ECC_DMA_W_SAFEMODE_EN;
    }
    else
    {
        XBYTE[ECC_MODE0] &= ~(ECC_DMA_WR_BYPASS_EN +
                              ECC_DMA_W_SAFEMODE_EN);
    }
}

/******************************************************************************/
void MDrv_Sys_SetECC(void)
{
    if (ENABLE_HKMCU_CODE_ECC)
    {
        XBYTE[ECC_MODE0] = ECC_CACHE_PREFETCH_EN;
        XBYTE[ECC_MISC0] = ECC_1ERR_RST | ECC_2ERR_RST | ECC_2ERR_INT_EN; // clear ERR status
        XBYTE[ECC_MISC0] = ECC_2ERR_INT_EN;

        // 8051 address
        MDrv_Write4Byte(ECC_8051_BASE_ADDR, ( CODE_MAP_BASE_ADR >> 3 ) );
        MDrv_Write4Byte(ECC_8051_END_ADDR, ((CODE_MAP_BASE_ADR+CODE_MAP_LEN - 1) >>3 ));

        // AEON address
        //MDrv_Write4Byte(ECC_AEON_BASE_ADDR,( CODE_MAP_BASE_ADR >> 3 ) ); // 0x00000000);
        //MDrv_Write4Byte(ECC_AEON_END_ADDR,((CODE_MAP_BASE_ADR+CODE_MAP_LEN - 1) >>3 ));  //((AEON_CODE_SIZE - 1) ) );

        // DMA address
        MDrv_Write4Byte(ECC_DMA_BASE_ADDR,( CODE_MAP_BASE_ADR >> 3 ) ); // 0x00000000);
        MDrv_Write4Byte(ECC_DMA_END_ADDR,((CODE_MAP_BASE_ADR+CODE_MAP_LEN - 1) >>3 )); // ((ECC_DMA_SIZE - 0x1)) );

        MDrv_Sys_SetInterrupt( EX1_ECC_DERR, ENABLE );

        DRVSYS(printf("ECC turn ON\r\n"));
    }
    else
    {
        XBYTE[ECC_MODE0] = ECC_DMA_WR_BYPASS_EN +
                           ECC_8051_R_BYPASS_EN +
                           ECC_AEON_R_BYPASS_EN +
                           ECC_CACHE_BYPASS_EN  +
                           ECC_DMA_W_SAFEMODE_EN;

        DRVSYS(printf("ECC turn OFF\r\n"));
    }
}

/******************************************************************************/
/******************************************************************************/
static void MDrv_Sys_Bonding_Init()
{

}

/******************************************************************************/
void MDrv_Sys_InitUartForXtalClk( char cOutputChar ) small
{
    if ( ENABLE_UART0 )
    {
        ADCON |= 0x80;
        S0RELL =  (UART_CLKREL(MCU_CLOCK_BOOT, UART0_BAUDRATE) & 0xff);
        S0RELH = ((UART_CLKREL(MCU_CLOCK_BOOT, UART0_BAUDRATE) >> 8) & 0x03);
        S0CON = 0x50;
        PCON |= 0x80;
        if ( STDOUT_DEVICE == IO_DEV_UART0 && cOutputChar )
            S0BUF = cOutputChar;
    }
    if ( ENABLE_UART1 )
    {
    	S1RELL =  (UART_CLKREL(MCU_CLOCK_BOOT, UART1_BAUDRATE) & 0xFF);
    	S1RELH = ((UART_CLKREL(MCU_CLOCK_BOOT, UART1_BAUDRATE) >> 8) & 0x03);
        S1CON = 0x90;   // mode 1, 8-bit UART, enable receive
        if ( STDOUT_DEVICE == IO_DEV_UART1 && cOutputChar )
            S1BUF = cOutputChar;
    }

// seven moses not need    XBYTE[0x1E03] |= 0x04;          // enable UART RX
}

// should not be necessary, remove later
void MDrv_Sys_UartControl(BOOLEAN bEnable)
{
    if(bEnable)
    {
        S0CON = 0x52;    // 01010010b
    }
    else
    {
        S0CON = 0x00;
    }
}

extern  void SwI2cTest(void );
//extern void HwI2cAccessTest(void);

/******************************************************************************/

void MDrv_Sys_Devices_Init(void)
{
//U32  i;
//for( i=0;i<0x30000;i++ );//jtagdelay

    MDrv_Sys_Bonding_Init();

    //SwI2cTest();

    MDrv_Sys_SetECC();

    /* Init IIC */
    MDrv_IIC_Init();   //HW IIC interface initial
    //HwI2cAccessTest();

    // Init I2C I/O expander, this must be after MDrv_IIC_Init()
    MDrv_ExGPIO_Init();

    // setup interrupt group priority
    IP0 = (((INT_GRP0_PRIO & _BIT0) ? 1 : 0) << 0) |
          (((INT_GRP1_PRIO & _BIT0) ? 1 : 0) << 1) |
          (((INT_GRP2_PRIO & _BIT0) ? 1 : 0) << 2) |
          (((INT_GRP3_PRIO & _BIT0) ? 1 : 0) << 3) |
          (((INT_GRP4_PRIO & _BIT0) ? 1 : 0) << 4) |
          (((INT_GRP5_PRIO & _BIT0) ? 1 : 0) << 5);

    IP1 = (((INT_GRP0_PRIO & _BIT1) ? 1 : 0) << 0) |
          (((INT_GRP1_PRIO & _BIT1) ? 1 : 0) << 1) |
          (((INT_GRP2_PRIO & _BIT1) ? 1 : 0) << 2) |
          (((INT_GRP3_PRIO & _BIT1) ? 1 : 0) << 3) |
          (((INT_GRP4_PRIO & _BIT1) ? 1 : 0) << 4) |
          (((INT_GRP5_PRIO & _BIT1) ? 1 : 0) << 5);
}

/******************************************************************************/
static void MDrv_Sys_InitialPll(void)
{
    // puts("\r\npower on atop");

    XBYTE[BK_ADC_ATOP_08_L]=0x06;     // MPLL enable
    XBYTE[BK_ADC_ATOP_0A_L]=PANEL_MPLL_M;


    DRVSYS(puts("\r\nTurn all clock ON...\r\n"));

    XBYTE[REG_CKG_MIU] =    (MIU_CLOCK_ENABLE ? MIU_CLK_ENABLE:MIU_CLK_DISABLE)|
                            (MIU_CLOCK_INVERT ? MIU_CLK_INVERT:MIU_CLK_NONINVERT)|
                            ((MIU_CLOCK_SEL == MIU_CLOCK_108MHZ) ? MIU_CLK_108MHZ:
                             (MIU_CLOCK_SEL == MIU_CLOCK_100MHZ) ? MIU_CLK_100MHZ:
                             (MIU_CLOCK_SEL == MIU_CLOCK_143MHZ) ? MIU_CLK_143MHZ:
                             (MIU_CLOCK_SEL == MIU_CLOCK_123MHZ) ? MIU_CLK_123MHZ:MIU_CLK_108MHZ);

    XBYTE[REG_CKG_TCK] = (TCK_CLOCK_ENABLE ? TCK_CLK_ENABLE:TCK_CLK_DISABLE)|
                             (TCK_CLOCK_INVERT ? TCK_CLK_INVERT:TCK_CLK_NONINVERT);

    XBYTE[REG_CKG_GE] = (GE_CLOCK_ENABLE ? GE_CLK_ENABLE:GE_CLK_DISABLE)|
                              (GE_CLOCK_INVERT ? GE_CLK_INVERT:GE_CLK_NONINVERT)|
                              ((GE_CLOCK_SEL == GE_CLOCK_123MHZ) ? GE_CLK_123MHZ:
                               (GE_CLOCK_SEL == GE_CLOCK_108MHZ) ? GE_CLK_108MHZ:
                               (GE_CLOCK_SEL == GE_CLOCK_86MHZ) ? GE_CLK_86MHZ:
                               (GE_CLOCK_SEL == GE_CLOCK_72MHZ) ? GE_CLK_72MHZ:GE_CLK_123MHZ);

    XBYTE[REG_CKG_GOP] = (GOP0_CLOCK_ENABLE ? GOP0_CLK_ENABLE:GOP0_CLK_DISABLE)|
                         (GOP0_CLOCK_INVERT ? GOP0_CLK_INVERT:GOP0_CLK_NONINVERT)|
                         ((GOP0_CLOCK_SEL == GOP_CLOCK_ODCLK) ? GOP0_CLK_ODCLK:
                          (GOP0_CLOCK_SEL == GOP_CLOCK_IDCLK1) ? GOP0_CLK_IDCLK1:
                          (GOP0_CLOCK_SEL == GOP_CLOCK_IDCLK2) ? GOP0_CLK_IDCLK2:
                          (GOP0_CLOCK_SEL == GOP_CLOCK_XTAL) ? GOP0_CLK_XTAL:GOP0_CLK_ODCLK)|
                         (GOP1_CLOCK_ENABLE ? GOP1_CLK_ENABLE:GOP1_CLK_DISABLE)|
                         (GOP1_CLOCK_INVERT ? GOP1_CLK_INVERT:GOP1_CLK_NONINVERT)|
                         ((GOP1_CLOCK_SEL == GOP_CLOCK_ODCLK) ? GOP1_CLK_ODCLK:
                          (GOP1_CLOCK_SEL == GOP_CLOCK_IDCLK1) ? GOP1_CLK_IDCLK1:
                          (GOP1_CLOCK_SEL == GOP_CLOCK_IDCLK2) ? GOP1_CLK_IDCLK2:
                          (GOP1_CLOCK_SEL == GOP_CLOCK_XTAL) ? GOP1_CLK_XTAL:GOP1_CLK_ODCLK);

    XBYTE[REG_CKG_VD] = (VD_CLOCK_ENABLE ? VD_CLK_ENABLE:VD_CLK_DISABLE)|
                            (VD_CLOCK_INVERT ? VD_CLK_INVERT:VD_CLK_NONINVERT)|
                            ((VD_CLOCK_SEL == VD_CLOCK_VD) ? VD_CLK_VD:
                             (VD_CLOCK_SEL == VD_CLOCK_0) ? VD_CLK_0:
                             (VD_CLOCK_SEL == VD_CLOCK_TESTMODE) ? VD_CLK_TESTMODE:
                             (VD_CLOCK_SEL == VD_CLOCK_XTAL) ? VD_CLK_XTAL:VD_CLK_VD);

    XBYTE[REG_CKG_VDS] = (VDMCU_CLOCK_ENABLE ? VDMCU_CLK_ENABLE:VDMCU_CLK_DISABLE)|