drvddc2bi.c

mstar 776 开发的车载dvd

////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2007 MStar Semiconductor, Inc.
// All rights reserved.
//
// Unless otherwise stipulated in writing, any and all information contained
// herein regardless in any format shall remain the sole proprietary of
// MStar Semiconductor Inc. and be kept in strict confidence
// (¨MStar Confidential Information〃) by the recipient.
// Any unauthorized act including without limitation unauthorized disclosure,
// copying, use, reproduction, sale, distribution, modification, disassembling,
// reverse engineering and compiling of the contents of MStar Confidential
// Information is unlawful and strictly prohibited. MStar hereby reserves the
// rights to any and all damages, losses, costs and expenses resulting therefrom.
//
// File Name: DDC2BI.c
// Description: For Slave I2C functions.
//
// Registers read and write command list:
// DATA WRITE : START + 0x6E + 0x10 + addrh + addrl + data + STOP
// DATA READ  : START + 0x6E + 0x10 + addrh + addrl + START + 0x6F + data +STOP
//
// Functions read and write command list:
// write contrast   : START + 0x6E + 0x20 +  01  +   xxh +   data  + STOP
// read  contrast   : START + 0x6E + 0x20 +  01  +   xxh +   START + 0x6F + (data) + STOP
// write Brightness : START + 0x6E + 0x20 +  02  +   xxh +   data  + STOP
// read  Brightness : START + 0x6E + 0x20 +  02  +   xxh +   START + 0x6F + (data) + STOP
// ON/OFF Panel set : START + 0x6E + 0x20 +  10  +   xxh +   0:OFF 1:ON  + STOP
// ON/OFF Panel Rd  : START + 0x6E + 0x20 +  10  +   xxh +   START + 0x6F + (data) + STOP
//
////////////////////////////////////////////////////////////////////////////////

#include "Analog_Reg.h"
#include "hwreg.h"
#include "drvglobal.h"
#include "drvddc2bi.h"
#include <intrins.h>

#if ENABLE_DDCCI

#define _DRVDDC2BI_C_

#if 1


#define D2bSetDebugPin() MDrv_WriteRegBit(BK_CHIPTOP_58_L,TRUE,BIT5)
#define D2bClrDebugPin() MDrv_WriteRegBit(BK_CHIPTOP_58_L,FALSE,BIT5)

#define D2B_SLAVE_ADDR_A0				0x6E

#define B_D2B_FF_INT_NUM_EMPTY			0x00
#define B_D2B_FF_INT_NUM_1				0x01
#define B_D2B_FF_INT_NUM_2				0x02
#define B_D2B_FF_INT_NUM_4				0x03
#define B_D2B_FF_INT_NUM				(B_D2B_FF_INT_NUM_EMPTY<<2)

#define D2B_WB_RP_A0					BK_DDC_00_L
 #define F_D2B_ENABLE					_BIT7
 #define B_D2B_ID_A0					(D2B_SLAVE_ADDR_A0>>1)
#define D2B_RB_WP_A0					BK_DDC_00_H
#define D2B_CTRL1_A0					BK_DDC_04_L
 #define F_D2B_RBUF_WPORT_PULSE_A0		_BIT7
#define D2B_CTRL2_A0					BK_DDC_04_H
#define D2B_ID_A0						BK_DDC_05_L
#define D2B_INT_FLAG_A0					BK_DDC_08_L
#define D2B_INT_MSK_A0					BK_DDC_0A_L
 #define B_D2B_INT_A0					~(F_D2B_INT_STOP|F_D2B_INT_READ|F_D2B_INT_WRITE|F_D2B_INT_8THIDBIT)
 #define B_D2B_FF_INT_A0				~(F_D2B_INT_STOP|F_D2B_INT_8THIDBIT)
 #define F_D2B_INT_SCL_HOLD				_BIT7
 #define F_D2B_INT_START				_BIT6
 #define F_D2B_INT_STOP					_BIT5
 #define F_D2B_INT_READ					_BIT4 // Write data into rbuf to clear
 #define F_D2B_INT_WRITE				_BIT3 // read data from wbuf to clear
 #define F_D2B_INT_8THIDBIT				_BIT2 // 1:Read ID
 #define F_D2B_INT_WADR					_BIT1 // 1:Data after the WADDR;0:Data isn't after the WADDR 
 #define F_D2B_INT_ID					_BIT0
#define D2B_INT_FORCE_A0				BK_DDC_0C_L
#define D2B_INT_CLR_A0					BK_DDC_0E_L
#define D2B_WBUF_RPORT_FF				BK_DDC_12_L

#define D2B_FF_INT_CTRL1				BK_DDC_13_L
 #define F_D2B_FF_USE					_BIT4
 #define F_D2B_FF_INT_NUM				(B_D2B_FF_INT_NUM<<2)
#define D2B_FF_INT_CTRL2				BK_DDC_13_H
 #define F_D2B_WBUF_RPORT_FF_RP			_BIT0
#define D2B_FF_INT_STATE1				BK_DDC_14_L
#define D2B_FF_INT_STATE2				BK_DDC_14_H
 #define F_D2B_WBUF_STATE				_BIT4
 #define F_D2B_FF_EMPTY					_BIT1
 #define F_D2B_FF_FULL					_BIT0

#define D2B_FF_INT_CTRL3				BK_DDC_15_L
 #define F_D2B_FF_NUM_INT_STS			_BIT4
 #define F_D2B_FF_NUM_INT_MSK			_BIT2
 #define F_D2B_FF_NUM_INT_CLR			_BIT0
#define D2B_RESET_A0					BK_DDC_3E_L

#define D2B_BUFFER_SIZE		256
#define D2B_DELAY_COUT	1
xdata U8 u8D2bStopFlag;
xdata U8 u8D2bRxBuffIndex;
xdata U8 u8D2bRxBuff[D2B_BUFFER_SIZE];
xdata U8 u8D2bTxBuffIndex;
xdata U8 u8D2bTxBuff[D2B_BUFFER_SIZE];



void MDrv_DDC2BI_FF_Init(void)
{
	U8 i;
	u8D2bStopFlag=0;
	u8D2bRxBuffIndex=0;
	u8D2bTxBuffIndex=0;

	MDrv_WriteRegBit(D2B_RESET_A0,FALSE,BIT7); //SW Reset DDC2BI
	MDrv_WriteRegBit(D2B_RESET_A0,TRUE,BIT7);

	MDrv_WriteByte(D2B_ID_A0,F_D2B_ENABLE|B_D2B_ID_A0); //ENABLE DDC2BI and SET ID 	
	MDrv_WriteByte(D2B_CTRL2_A0,0x00);
	MDrv_WriteByte(D2B_INT_FORCE_A0,0x00);
	MDrv_WriteByte(D2B_INT_MSK_A0,B_D2B_FF_INT_A0);
	MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
	MDrv_WriteByte(D2B_INT_CLR_A0,0x00);

	MDrv_WriteRegBit(D2B_FF_INT_CTRL3,DISABLE,F_D2B_FF_NUM_INT_MSK);
	MDrv_WriteByte(D2B_FF_INT_CTRL1,F_D2B_FF_USE|F_D2B_FF_INT_NUM);

	MDrv_WriteRegBit(BK_DDC_22_H,TRUE,BIT6);
	MDrv_WriteRegBit(BK_DDC_23_L,TRUE,BIT7);

	//enable interrupt mask
	MDrv_WriteRegBit(BK_2B_0D_H,FALSE,BIT2);

	for(i=0;i<255;i++)
		u8D2bTxBuff[i]=i;

D2bClrDebugPin();
}

void MDrv_DDC2BI_FF_Int(void)
{
	U8 i;
	U8 u8D2bState;
	U8 u8D2bFFState;

D2bSetDebugPin();

	u8D2bState=MDrv_ReadByte(D2B_INT_FLAG_A0);
	MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
	MDrv_WriteByte(D2B_INT_CLR_A0,0x00);

	u8D2bFFState=MDrv_ReadByte(D2B_FF_INT_CTRL3);
	MDrv_WriteRegBit(D2B_FF_INT_CTRL3,ENABLE,F_D2B_FF_NUM_INT_CLR);
	MDrv_WriteRegBit(D2B_FF_INT_CTRL3,DISABLE,F_D2B_FF_NUM_INT_CLR);

	if(u8D2bState&F_D2B_INT_8THIDBIT)
	{
		u8D2bTxBuffIndex=0;
		while(!MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_FF_FULL))
		{
			MDrv_WriteByte(D2B_RB_WP_A0,u8D2bTxBuff[u8D2bTxBuffIndex++]);
			MDrv_WriteRegBit(D2B_CTRL1_A0,TRUE,F_D2B_RBUF_WPORT_PULSE_A0);
			for(i=0;i<D2B_DELAY_COUT;i++)
				_nop_();
		}
		u8D2bTxBuffIndex--;
		MDrv_WriteRegBit(D2B_FF_INT_CTRL3,ENABLE,F_D2B_FF_NUM_INT_CLR);
		MDrv_WriteRegBit(D2B_FF_INT_CTRL3,DISABLE,F_D2B_FF_NUM_INT_CLR);
	}
	else if(u8D2bFFState&F_D2B_FF_NUM_INT_STS)
	{
		if(MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_WBUF_STATE))
		{
			while(!MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_FF_EMPTY))
			{
				u8D2bRxBuff[u8D2bRxBuffIndex++]=MDrv_ReadByte(D2B_WBUF_RPORT_FF);
				MDrv_WriteRegBit(D2B_FF_INT_CTRL2,ENABLE,F_D2B_WBUF_RPORT_FF_RP);

				for(i=0;i<D2B_DELAY_COUT;i++)
					_nop_();
			}
		}
		else
		{
			while(!MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_FF_FULL))
			{
				MDrv_WriteByte(D2B_RB_WP_A0,u8D2bTxBuff[u8D2bTxBuffIndex++]);
				MDrv_WriteRegBit(D2B_CTRL1_A0,TRUE,F_D2B_RBUF_WPORT_PULSE_A0);
				for(i=0;i<D2B_DELAY_COUT;i++)
					_nop_();
			}
			u8D2bTxBuffIndex--;
			MDrv_WriteRegBit(D2B_FF_INT_CTRL3,ENABLE,F_D2B_FF_NUM_INT_CLR);
			MDrv_WriteRegBit(D2B_FF_INT_CTRL3,DISABLE,F_D2B_FF_NUM_INT_CLR);
		}
	}
	else if(u8D2bState&F_D2B_INT_STOP)
	{
		if(MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_WBUF_STATE))
		{
			while(!MDrv_ReadRegBit(D2B_FF_INT_STATE2,F_D2B_FF_EMPTY))
			{
				u8D2bRxBuff[u8D2bRxBuffIndex++]=MDrv_ReadByte(D2B_WBUF_RPORT_FF);
				MDrv_WriteRegBit(D2B_FF_INT_CTRL2,ENABLE,F_D2B_WBUF_RPORT_FF_RP);

				for(i=0;i<D2B_DELAY_COUT;i++)
					_nop_();
			}
		}

#if 1
		if(u8D2bRxBuffIndex)
		{
			u8D2bRxBuffIndex=0;
			u8D2bStopFlag=1;
		}
#else
			u8D2bStopFlag=1;
#endif
	}

D2bClrDebugPin();

}

void MDrv_DDC2BI_Init(void)
{
	U8 i;
	u8D2bStopFlag=0;
	u8D2bRxBuffIndex=0;
	u8D2bTxBuffIndex=0;

	MDrv_WriteRegBit(D2B_RESET_A0,FALSE,BIT7); //SW Reset DDC2BI
	MDrv_WriteRegBit(D2B_RESET_A0,TRUE,BIT7);

	MDrv_WriteByte(D2B_ID_A0,F_D2B_ENABLE|B_D2B_ID_A0); //ENABLE DDC2BI and SET ID 	
	MDrv_WriteByte(D2B_CTRL2_A0,0x00);
	MDrv_WriteByte(D2B_INT_FORCE_A0,0x00);
	MDrv_WriteByte(D2B_INT_MSK_A0,B_D2B_INT_A0);
	MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
	MDrv_WriteByte(D2B_INT_CLR_A0,0x00);

	MDrv_WriteRegBit(D2B_FF_INT_CTRL3,ENABLE,F_D2B_FF_NUM_INT_MSK);

	MDrv_WriteRegBit(BK_DDC_22_H,TRUE,BIT6);
	MDrv_WriteRegBit(BK_DDC_23_L,TRUE,BIT7);

	//enable interrupt mask
	MDrv_WriteRegBit(BK_2B_0D_H,FALSE,BIT2);

	for(i=0;i<255;i++)
		u8D2bTxBuff[i]=i;

D2bClrDebugPin();
}



void MDrv_DDC2BI_Int(void)
{
	U8 i;
	U8 u8D2bState;

D2bSetDebugPin();

	u8D2bState=MDrv_ReadByte(D2B_INT_FLAG_A0);
	MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
	MDrv_WriteByte(D2B_INT_CLR_A0,0x00);

	if(u8D2bState&F_D2B_INT_WRITE)
	{
		u8D2bRxBuff[u8D2bRxBuffIndex++]=MDrv_ReadByte(D2B_WB_RP_A0);

//		MDrv_WriteRegBit(D2B_FF_INT_CTRL2,ENABLE,F_D2B_WBUF_RPORT_FF_RP);
	}
	else if(u8D2bState&F_D2B_INT_8THIDBIT)
	{
		u8D2bTxBuffIndex=0;
		MDrv_WriteByte(D2B_RB_WP_A0,u8D2bTxBuff[u8D2bTxBuffIndex++]);
		MDrv_WriteRegBit(D2B_CTRL1_A0,TRUE,F_D2B_RBUF_WPORT_PULSE_A0);

		for(i=0;i<D2B_DELAY_COUT;i++)
			_nop_();

		MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
		MDrv_WriteByte(D2B_INT_CLR_A0,0x00);
	}
	else if(u8D2bState&F_D2B_INT_READ)
	{
		MDrv_WriteByte(D2B_RB_WP_A0,u8D2bTxBuff[u8D2bTxBuffIndex++]);
		MDrv_WriteRegBit(D2B_CTRL1_A0,TRUE,F_D2B_RBUF_WPORT_PULSE_A0);

		for(i=0;i<D2B_DELAY_COUT;i++)
			_nop_();

		MDrv_WriteByte(D2B_INT_CLR_A0,0xFF);
		MDrv_WriteByte(D2B_INT_CLR_A0,0x00);
	}
	else if(u8D2bState&F_D2B_INT_STOP)
	{

#if 1
		if(u8D2bRxBuffIndex)
		{
			u8D2bRxBuffIndex=0;
			u8D2bStopFlag=1;
		}
#else
			u8D2bStopFlag=1;
#endif
	}

D2bClrDebugPin();

}
#else

/********************
* INCLUDE FILES     *
*********************/
#include <stdio.h>
#include "board.h"
#include "mreg51.h"
#include "datatype.h"
#include "hwreg.h"
#include "drvsys.h"
#include "Analog_Reg.h"
#include "drvScaler.h"
#include "drviic.h"
#include "drvglobal.h"
#include "drviic.h"
#include "drvtimer.h"
#include "drvddc2bi.h"

#include "drvtimer.h"

#include "ddc2bi_cus.h"
U8 DDCTemp;

U8 drvDDC2BI_AlignControl_NULL(U8 *pDDCBuffData) { DDCTemp = *pDDCBuffData; return 0;}
#ifndef CB_DDC2B_SRC_STANDARD
#define CB_DDC2B_SRC_STANDARD           drvDDC2BI_AlignControl_NULL
#endif
#ifndef CB_DDC2B_SRC_CUSTOMER
#define CB_DDC2B_SRC_CUSTOMER           drvDDC2BI_AlignControl_NULL
#endif

// functions in this file are called by MDrv_DDC2BI_IIC() which
// is called from EX1_ISR, and should be register bank independent
#pragma NOAREGS

#define DDC_MSG(x) //x

code BYTE nullMsg1[3] =
{
    0x6e, 0x80, 0xbe
};