📄 mst7702_socket_gpio.c
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#include "mreg51.h"
#include "sysinfo.h"
#include "hwreg.h"
#include "drvuart.h"
#include "drvmiu.h"
#include "drvsys.h"
#include "Analog_Reg.h"
#include "drvGlobal.h"
#include "drvISR.h"
#include "drviic.h"
#include <stdio.h>
#include "DrvGpio.h"
//---------------------------------------------------------------------
#define IR_PORT_SEL (BIT2|BIT3) //IR_USE_PAD_IRIN2/INT_USE_PAD_INT2
#define IRIN2_INT2_IS_GPIO (BIT0|BIT1)
#define IRIN_INT_IS_GPIO (BIT6|BIT7)
#if 1// kevin 20070822
//----------------------------------------------------------------------
// (GPIO interface / GPIO~6) (DTCON share GPIO46)
// default set as Input function except GPIO5 (REG1EBCh = 0x20 @ power on)
//----------------------------------------------------------------------
#define DTCON_PAD_IS_GPIO FALSE // TRUE
#define GPIO4_IS_PWM TRUE
#define GPIO5_IS_PWM FALSE
#define GPIO6_IS_PWM FALSE
#define GPIO_PAD_SHARE_PWM GPIO4_IS_PWM//(GPIO4_IS_PWM|GPIO5_IS_PWM|GPIO6_IS_PWM)
#define GPIO_PAD_IS_OUTPUT 0x7F // BIT0~BIT6, (BIT0|BITX...)
#define GPIO_PAD_IS_INPUT (~GPIO_PAD_IS_OUTPUT) // BIT0~BIT6, (BIT0|BITX...)
void InitNormalDTCONPort(void)
{
// GPIO 0~6
XBYTE[REG_MUX_DTCON_GPIO_SEL] &= GPIO_PAD_IS_INPUT;
XBYTE[REG_MUX_DTCON_GPIO_SEL] |= GPIO_PAD_IS_OUTPUT;
#if (GPIO_PAD_SHARE_PWM)
#if GPIO4_IS_PWM
XBYTE[REG_MUX_DTCON_GPIO_SEL] &= ~_BIT4;
XBYTE[REG_MUX_TOP6_GPIO] |= _BIT4;
#endif
#if GPIO5_IS_PWM
XBYTE[REG_MUX_DTCON_GPIO_SEL] &= ~_BIT5;
XBYTE[REG_MUX_CONFIG_5] &= ~_BIT4;
#endif
#if GPIO6_IS_PWM
XBYTE[REG_MUX_DTCON_GPIO_SEL] &= ~_BIT6;
XBYTE[REG_MUX_CONFIG_5] &= ~_BIT5;
#endif
XBYTE[REG_CENTRAL_EN] &= ~_BIT1;
#endif
// GPIO46 or DTCON
#if (DTCON_PAD_IS_GPIO == TRUE)
XBYTE[REG_MUX_DTCON_GPIO_SEL] |= BIT7; // 1: gpio, 0: DTCON
#else
XBYTE[REG_MUX_DTCON_GPIO_SEL] &= ~BIT7; // 1: gpio, 0: DTCON
#endif
//XBYTE[REG_CENTRAL_EN] &= ~(GPIO_COEN); // 1 : tri-state, 0 : out enable
}
//----------------------------------------------------------------------
// (Front interface / GPIO7~8) share
// default set as VD sync out function
// REG_CENTRAL_EN = 1 --> Use GPIO52~53 ()
// REG_CENTRAL_EN = 0 --> Use GPIO7~8 ()
//----------------------------------------------------------------------
#define PAD_VD_CLKO BIT0 // GPIO7
#define PAD_VD_FB BIT1 // GPIO8
#define FRONT_PAD_IS_GPIO (PAD_VD_CLKO|PAD_VD_FB)
#define FRONT_PAD_IS_SYNC ~(FRONT_PAD_IS_GPIO)
#define FRONT_GPIO_IS_OUTPUT (PAD_VD_CLKO|PAD_VD_FB)
#define FRONT_GPIO_IS_INPUT (~(FRONT_GPIO_IS_OUTPUT)&0x03)
#define FRONT_SEL_GPIO78 1// 1: GPIO7~8, 0: GPIO52~53
void InitialFrontPort(void)
{
#if (FRONT_PAD_IS_GPIO == TRUE)
#if (FRONT_SEL_GPIO78 == TRUE)// GPIO7~8
XBYTE[REG_CENTRAL_EN] &= ~(VD_SWRGBOUT_EN);
XBYTE[REG_MUX_VD_GPIO_SEL3] |= FRONT_PAD_IS_GPIO;// 1: gpio, 0: Sync (CLK, FB)
#else// GPIO52~53
XBYTE[REG_CENTRAL_EN] |= (VD_SWRGBOUT_EN);
#endif
#else
XBYTE[REG_CENTRAL_EN] &= ~(VD_SWRGBOUT_EN); // Sync (CLK, FB)
XBYTE[REG_MUX_VD_GPIO_SEL3] &= FRONT_PAD_IS_SYNC;// 1: gpio, 0: Sync (CLK, FB)
#endif
//XBYTE[REG_CENTRAL_EN] &= ~(VD_SYNCO_COEN); // 1 : tri-state, 0 : out enable
}
//----------------------------------------------------------------------
// (Digital input interface / GPIO9~33) share
// default set as VD data input function
//----------------------------------------------------------------------
#define DIGITAL0_PAD_IS_GPIO FALSE // TRUE
#define DIGITAL0_GPIO_IS_OUTPUT 0xFF
#define DIGITAL0_GPIO_IS_INPUT ~(DIGITAL0_GPIO_IS_OUTPUT)
#define DIGITAL1_PAD_IS_GPIO FALSE // TRUE
#define DIGITAL1_GPIO_IS_OUTPUT 0xFF
#define DIGITAL1_GPIO_IS_INPUT ~(DIGITAL1_GPIO_IS_OUTPUT)
#define DIGITAL2_PAD_IS_GPIO FALSE // TRUE
#define DIGITAL2_GPIO_IS_OUTPUT 0xFF
#define DIGITAL2_GPIO_IS_INPUT ~(DIGITAL2_GPIO_IS_OUTPUT)
#define VSYNC2_I_PAD BIT2
#define HSYNC2_I_PAD BIT3
#define DIGITAL_SYNC_PAD_IS_GPIO FALSE // TRUE
#define DIGITAL_SYNC_GPIO_IS_OUTPUT (VSYNC2_I_PAD|HSYNC2_I_PAD)
#define DIGITAL_SYNC_GPIO_IS_INPUT ~(DIGITAL_SYNC_GPIO_IS_OUTPUT)
void InitialDigitalInputPort(void)
{
#if (DIGITAL0_PAD_IS_GPIO == TRUE)// VD0~7 or GPIO11~18
XBYTE[REG_MUX_VD_GPIO_SEL0] &= DIGITAL0_GPIO_IS_INPUT;
XBYTE[REG_MUX_VD_GPIO_SEL0] |= DIGITAL0_GPIO_IS_INPUT;
#else
XBYTE[REG_MUX_VD_GPIO_SEL0] = 0x00;
#endif
#if (DIGITAL1_PAD_IS_GPIO == TRUE)// VD8~15 or GPIO19~26
XBYTE[REG_MUX_VD_GPIO_SEL1] &= DIGITAL1_GPIO_IS_INPUT;
XBYTE[REG_MUX_VD_GPIO_SEL1] |= DIGITAL1_GPIO_IS_INPUT;
#else
XBYTE[REG_MUX_VD_GPIO_SEL1] = 0x00;;
#endif
#if (DIGITAL2_PAD_IS_GPIO == TRUE)// VD16~23 or GPIO27~33
XBYTE[REG_MUX_VD_GPIO_SEL2] &= DIGITAL2_GPIO_IS_INPUT;
XBYTE[REG_MUX_VD_GPIO_SEL2] |= DIGITAL2_GPIO_IS_INPUT;
#else
XBYTE[REG_MUX_VD_GPIO_SEL2] = 0x00;
#endif
#if (DIGITAL_SYNC_PAD_IS_GPIO == TRUE)// H/V sync2 or GPIO9~10
XBYTE[REG_MUX_VD_GPIO_SEL3] &= DIGITAL_SYNC_GPIO_IS_INPUT;
XBYTE[REG_MUX_VD_GPIO_SEL3] |= DIGITAL_SYNC_GPIO_IS_OUTPUT;
#endif
//XBYTE[REG_CENTRAL_EN] &= ~(GPIO_COEN); // 1 : tri-state, 0 : out enable
}
//----------------------------------------------------------------------
// (Digital input interface / GPIO34~46) share
// default set as Panel signal output function
//----------------------------------------------------------------------
#define PANEL_PAD_IS_GPIO FALSE
#define PAD_HSYNCO BIT0
#define PAD_VSYNCO BIT1
#define PAD_DEO BIT2
#define PAD_CLKO BIT3
#define PANEL_SYNC_GPIO_IS_OUTPUT 0x0F//(PAD_HSYNC|PAD_VSYNC...)
#define PAD_ROUT4 BIT6
#define PAD_ROUT5 BIT7
#define PAD_ROUT6 BIT4
#define PAD_ROUT7 BIT5
#define PANEL_DATAR1_GPIO_IS_OUTPUT 0xF0// (PAD_ROUT4|PAD_ROUT5...)
#define PAD_ROUT0 BIT2
#define PAD_ROUT1 BIT3
#define PAD_ROUT2 BIT0
#define PAD_ROUT3 BIT1
#define PANEL_DATAR0_GPIO_IS_OUTPUT 0x0F// (PAD_ROUT0|PAD_ROUT1...)
void InitialPanelPort(void)
{
// GPIO34~41
#if (PANEL_PAD_IS_GPIO)
// GPIO34~37
XBYTE[0x309B] &= 0xF0;
XBYTE[0x309B] |= PANEL_DATAR0_GPIO_IS_OUTPUT;
XBYTE[0x308D] |= 0x0F; //1: GPIO, 0: Panel Signal
// GPIO38~41
XBYTE[0x309A] &= 0x0F;
XBYTE[0x309A] |= PANEL_DATAR1_GPIO_IS_OUTPUT;
XBYTE[0x308C] |= 0xF0; // GPIO38~41 //1: GPIO, 0: Panel Signal
#else
XBYTE[0x308C] &= 0x0F; // GPIO38~41 //1: GPIO, 0: Panel Signal
XBYTE[0x308D] &= 0xF0; // GPIO34~37 //1: GPIO, 0: Panel Signal
#endif
// GPIO 42~45
#if (PANEL_PAD_IS_GPIO)
XBYTE[0x309A] &= 0xF0;
XBYTE[0x309A] |= PANEL_SYNC_GPIO_IS_OUTPUT;
XBYTE[0x308C] |= 0x0F; // GPIO42~45 //1: GPIO, 0: Panel Signal
#else
XBYTE[0x308C] &= 0xF0; // GPIO42~45 //1: GPIO, 0: Panel Signal
#endif
}
//----------------------------------------------------------------------
// (Eembeded MCU port / GPIO47~51) share
// default set as Panel signal output function
//----------------------------------------------------------------------
#define SAR_PAD_IS_GPIO FALSE
#define SAR_PAD0 BIT0
#define SAR_PAD1 BIT1
#define SAR_PAD2 BIT2
#define SAR_PAD3 BIT3
#define SAR_GPIO_CH_SEL 0//(SAR_PAD0|SAR_PAD1...)
#define SAR_GPIO_IS_OUTPUT 0x0F// (SAR_PAD0|SAR_PAD1...)
#define SAR_GPIO_IS_INPUT ((~SAR_GPIO_IS_OUTPUT)&0x0F)
void InitialMCUPort(void)
{
#if (SAR_PAD_IS_GPIO)
XBYTE[0x3A20] = (~SAR_GPIO_CH_SEL) & 0x0F; // 1: SAR, 0: GPIO // [3:0]
XBYTE[0x3A20] |= (SAR_GPIO_IS_INPUT<<4);// 1: GPI, 0: GPO // [7:4]
#else
XBYTE[0x3A20] |= 0xFF; // 1: SAR, 0: GPIO
#endif
}
#endif// kevin 20070822
///---------------------------------------------------------------------
/// initial gpio0 for RGB/YPbPr source switch
/// default set to "0" : RGB input
///---------------------------------------------------------------------
void Iniital_USB_OCD_N( void ) //gpio_0 set to output
{
XBYTE[REG_MUX_CONFIG_3] &= ~(SECOND_UART_MODE); //UART1 not enable
XBYTE[REG_MUX_FUNC_SEL1] &= (~CEC_MODE); //XBYTE[0x1ea1] &=0xe7; //disable CEC
}
//---------------------------------------------------------------------
//---------------------------------------------------------------------
void InitialSaturn2_Pin134 (void ) //pin 134 RGB/YPbPr
{
XBYTE[REG_MUX_FUNC_SEL1] &= (~CEC_MODE);
Switch_YPbPr1(); //default connect to RGB
}
//---------------------------------------------------------------------
///In MST37K_D01A demo set(2166)
///Remote_control IR connect to IR2
//pin 178/179
//---------------------------------------------------------------------
static void Initial_IR_Port( void )
{
XBYTE[REG_MUX_CONFIG_2] |= IR_PORT_SEL;
//XBYTE[REG_MUX_FUNC_SEL2]=(XBYTE[REG_MUX_FUNC_SEL2] & 0x3f )|IRIN_INT_IS_GPIO;
}
//---------------------------------------------------------------------
// (UART1 TX1, RX1 / PWM3, 4) share
// TX1 - PWM3, RX1 - PWM4
//---------------------------------------------------------------------
#define UART1_PAD_IS_PWM FALSE
void InitialSaturn2_UART1_Port ( void )
{
#if UART1_PAD_IS_PWM
XBYTE[REG_MUX_CONFIG_5] &= ~(_BIT4+_BIT5);// 0: PWM, 1: UART
XBYTE[REG_MUX_UART_PWM_SEL] &= ~_BIT6;
#else
XBYTE[REG_MUX_CONFIG_5] |= (_BIT4+_BIT5);// 0: PWM, 1: UART
XBYTE[REG_MUX_UART_PWM_SEL] |= _BIT6;
#endif
}
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
/*void InitialSaturn2_PCI_Port(void) //PCI is GPIO
{
XBYTE[REG_MUX_FUNC_SEL0] &= (~ATCON_SETTING);
XBYTE[REG_MUX_PCI]=(XBYTE[REG_MUX_PCI] & 0xc0) | PCI_GPIO_ENABLE; // PCI_AD0~AD7 is GPIO
XBYTE[REG_MUX_CONFIG_2] &= (~PCI_CONFIG);
XBYTE[REG_PCI_GPIO_OE_0]=PCI_GPIO_SETTING;
} //*/
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
void Initial_TconPort( void )
{
//inital pin 2~6 atcon 1~6
XBYTE[REG_MUX_FUNC_SEL0] &= ~BIT1; //PWM3_setting=0;
XBYTE[REG_MUX_FUNC_SEL0] &= (~ ( BIT5|BIT4 ) ); //DTCON=00b;
XBYTE[REG_MUX_FUNC_SEL0] &= (~ BIT6); //TCON_IS_GPIO=0;
XBYTE[REG_MUX_FUNC_SEL0] = (XBYTE[REG_MUX_FUNC_SEL0] & 0xf3 ) | BIT2; // ATCON mode=1;
}
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//---------------------------------------------------------------------
void Mst_GPIO_Initial( void )
{
puts("\r\nGPIO Init...");// kevin test
InitNormalDTCONPort();// kevin
Iniital_USB_OCD_N();
InitialSaturn2_Pin134();
Initial_IR_Port();
InitialSaturn2_UART1_Port();
//initial Tcon
Initial_TconPort();
InitialDigitalInputPort();// kevin 20070904
InitialFrontPort();// kevin 20070904
InitialMCUPort();// kevin 20070904
InitialPanelPort();// kevin 20070904
//-----------------------------------------------------------------------
//MDrv_Write2ByteA(0x1E5F,0x0000); // Turn on Center OEN control, After H/W reset.
XBYTE[0x1EBE] = 0x00;
#if (MOSES_CHIP_TYPE == MOSES_CHIP_MST7701)
//MDrv_Write2ByteA(0x1E5F,0x0000); // GPO central output enable. TCON 1:216Pin 0:176Pin
XBYTE[0x1EBF] = 0x00;
XBYTE[0x2E22] = 0x00;// kevin 071102_2
//puts("\r\nGPIO MOSES_CHIP_MST7701");// kevin test
#elif (MOSES_CHIP_TYPE == MOSES_CHIP_MST7702)
//MDrv_Write2ByteA(0x1E5F,0x0800); // GPO central output enable. TCON 1:216Pin 0:176Pin
XBYTE[0x1EBF] = 0x08 | _BIT2; // kevin 080102
XBYTE[0x2E22] = 0x80;// kevin 071102_2
//puts("\r\nGPIO MOSES_CHIP_MST7702");// kevin test
#endif
//-----------------------------------------------------------------------
/*
#if (PANEL_ATCON)
//MDrv_Write2ByteA(0x3059,0x0010); // Selection ATCON pad.
XBYTE[0x30B2] = 0x10;
#elif (PANEL_DTCON)
//MDrv_Write2ByteA(0x3059,0x0001); // Selection DTCON pad.
XBYTE[0x30B2] = 0x01;
#endif
XBYTE[0x30B3] = 0x00;
*/
//
Power_On();
}
//---------------------------------------------------------------------
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