mst037a_d01_gpio.c

mstar 776 开发的车载dvd

#include "mreg51.h"
#include "sysinfo.h"
#include "hwreg.h"
#include "drvuart.h"
#include "drvmiu.h"
#include "drvsys.h"
#include "Analog_Reg.h"
#include "drvGlobal.h"
#include "drvISR.h"
#include "drviic.h"

#include <stdio.h>

#include "DrvGpio.h"

//---------------------------------------------------------------------
#define IR_PORT_SEL                 IR_USE_PAD_IRIN

#define HS_VS_VD_DE_IO_SETTING      (BIT0)  //USB_OCD_N is input
#define SET_B0_B1_IO_MODE           0x00    //BIT3,BIT2=00b
#define SET_G4_G5_IO_MODE           (BIT1|BIT0)  //set to input mode

#define PCI_GPIO_SETTING            0x00        //define input only


//---------------------------------------------------------------------
//In MST demo set(2338)
//INT/IR is gpio, remote_control IR connect to IR2
//---------------------------------------------------------------------
void InitialSaturn2_IR_Port( void )
{
    XBYTE[REG_MUX_CONFIG_2] |= IR_PORT_SEL;
}
//---------------------------------------------------------------------
void InitialSaturn2_UART1_Port(void )	  //as UART1
{
    //UART 1
    //printf("initial UArt1 port\n");
    XBYTE[REG_MUX_CONFIG_3]   = (XBYTE[REG_MUX_CONFIG_3] & 0xfc) | SECOND_UART_MODE_1;  //0xc2;  //UART 1 to pad_lhs and pad_Lvs, and I2s_mute to pad_pci_ad8
    XBYTE[REG_MUX_FUNC_SEL1] &= (~CEC_MODE);  //XBYTE[0x1ea1] &=0xe7;   //disable CEC
    XBYTE[REG_P1_ENABLE] &= (~BIT7 );         //XBYTE[0x1ea4] &=0x7f;   //disable P1_7
    XBYTE[REG_MUX_UART_JTAG] |= UART1_SEL_51_UART1;  //XBYTE[ 0x1eaa] |=0x20;
}
//---------------------------------------------------------------------
void InitialSaturn2_Pin134 (void )	  //pin 134 cec
{
        XBYTE[REG_MUX_FUNC_SEL1] |= (CEC_MODE);
        XBYTE[REG_MUX_FUNC_SEL3]&=(~FLHWE_IS_GPIO);
        XBYTE[REG_MUX_CONFIG_4]  &= (~FCIE_CONFIG) ;
}
//---------------------------------------------------------------------
void InitialLVDS_B0_B1_IsGpio ( void )
{
    XBYTE[REG_SEL_TTL_1]  |= 0x08;  //bit 3 =0;
    XBYTE[ODD_IS_GPIO_3]  |= 0x0c;  //PAD_b_ODD0/PAD_b_ODD1 is GPIO
    XBYTE[ODD_GPO_SEL_3]  |= 0x0c;  //

    //define B0/b1 gpio is output port
    XBYTE[ODD_GPO_OEZ_3] = (XBYTE[ODD_GPO_OEZ_3] & 0xf3)| SET_B0_B1_IO_MODE;
}
//---------------------------------------------------------------------
//---------------------------------------------------------------------
void InitialLVDS_G4_G5_IsGpio ( void )
{
    XBYTE[REG_SEL_TTL_0 ] |= 0x20;      //bit 5 =0;
    XBYTE[ODD_IS_GPIO_1]  |= 0xc0;      //PAD_g_ODD4/PAD_g_ODD5 is GPIO
    XBYTE[ODD_GPO_SEL_1]  |= 0xc0;      //
    XBYTE[ODD_GPO_OEZ_2] = (XBYTE[ODD_GPO_OEZ_2] & 0xfc)| SET_G4_G5_IO_MODE;
}
//---------------------------------------------------------------------
void InitialLVDS_HS_VS_VE_DE_IsGpio( void )   // HS,VS,Clk,Ve is gpio
{
    XBYTE[ODD_IS_GPIO_0]  |= 0x0f;
    XBYTE[ODD_GPO_SEL_0]  |= 0x0f;
    XBYTE[ODD_GPO_OEZ_0]  =( XBYTE[ODD_GPO_OEZ_0] & 0xf0) | HS_VS_VD_DE_IO_SETTING;
}
//---------------------------------------------------------------------
void IntialSaturn2_TS_Port(void)	 //TS0 interface
{
   XBYTE[REG_MUX_CONFIG_0] |= TS0_IS_TS0;

   XBYTE[REG_MUX_CONFIG_0] &= ~( TS0_IS_DI );
   XBYTE[REG_MUX_FUNC_SEL3]&= ~( TS0_IS_GPIO );
   XBYTE[REG_MUX_FUNC_SEL6]&= ~( DHC_DFT_MODE);
   XBYTE[REG_MUX_CONFIG_5] &= ~( DSPE_JTAG_MODE );
}
//---------------------------------------------------------------------
//---------------------------------------------------------------------
void InitialSaturn2_I2S_Port( void )
{
    XBYTE[REG_MUX_FUNC_SEL3]&=( ~I2S_IS_GPIO );
    XBYTE[REG_MUX_CONFIG_3] = ( XBYTE[REG_MUX_CONFIG_3] & 0x3f ) | I2S_MUTE_MODE_1;    //I2sMUTE pin
}
//---------------------------------------------------------------------
void InitialSaturn2_PCI_Port(void)		//PCI is GPIO
{
    XBYTE[REG_MUX_FUNC_SEL0] &= (~ATCON_SETTING);

    XBYTE[REG_MUX_PCI]=(XBYTE[REG_MUX_PCI] & 0xc0) | PCI_GPIO_ENABLE; // PCI_AD0~AD7 is GPIO
    XBYTE[REG_MUX_CONFIG_2] &= (~PCI_CONFIG);
    XBYTE[REG_PCI_GPIO_OE_0]=PCI_GPIO_SETTING;
}
//---------------------------------------------------------------------
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//---------------------------------------------------------------------

//---------------------------------------------------------------------
void InitialSaturn2_DI_Port(void)		//to BT656 interface
{
    //DI_PAD_IS_BT656
    XBYTE[REG_MUX_FUNC_SEL3]  &= ( ~DI_IS_GPIO );
    XBYTE[REG_MUX_CONFIG_0] = (XBYTE[REG_MUX_CONFIG_0] & 0xE1 )|DI_MODE_IS_BT656;
}

//---------------------------------------------------------------------
void Mst_GPIO_Initial( void )
{
	//gpio port
	InitialSaturn2_DI_Port();

	InitialSaturn2_IR_Port();
	InitialSaturn2_UART1_Port();
	InitialSaturn2_Pin134();

	//mod lvds gpio
    InitialLVDS_B0_B1_IsGpio();
    InitialLVDS_G4_G5_IsGpio();
    InitialLVDS_HS_VS_VE_DE_IsGpio();

	//TS0 port
	IntialSaturn2_TS_Port();

    //PCI port as GPIO
	InitialSaturn2_PCI_Port();

	//i2s interface
	InitialSaturn2_I2S_Port();
}
//---------------------------------------------------------------------