📄 sys.a51
字号:
;///////////////////////////////////////////////////////////////////////////////
;
; Copyright (c) 2006-2007 MStar Semiconductor, Inc.
; All rights reserved.
;
; Unless otherwise stipulated in writing, any and all information contained
; herein regardless in any format shall remain the sole proprietary of
; MStar Semiconductor Inc. and be kept in strict confidence
; (¨MStar Confidential Information〃) by the recipient.
; Any unauthorized act including without limitation unauthorized disclosure,
; copying, use, reproduction, sale, distribution, modification, disassembling,
; reverse engineering and compiling of the contents of MStar Confidential
; Information is unlawful and strictly prohibited. MStar hereby reserves the
; rights to any and all damages, losses, costs and expenses resulting therefrom.
;
;///////////////////////////////////////////////////////////////////////////////
REG_SPI_START_0 EQU 0x1014
REG_SPI_START_1 EQU 0x1010
REG_SPI_END_0 EQU 0x1016
REG_SPI_END_1 EQU 0x1012
REG_CACHE_START_0 EQU 0x100C
REG_CACHE_START_1 EQU 0x1008
REG_CACHE_END_0 EQU 0x100E
REG_CACHE_END_1 EQU 0x100A
REG_CODE_FETCH EQU 0x1018 ; Code fetch configuration
REG_CODE_BANK EQU 0x1019 ; Current code bank
REG_CACHE_BASE EQU 0x2B80 ; Code fetch base address in MIU (unit: 64kbytes)
REG_CACHE_BYPASS EQU 0x2BA0
REG_SDR_XD_MAP_1 EQU 0x2BCC
// multiple DPTR
DPS DATA 0x92
// MDU
MD0 DATA 0xE9
MD1 DATA 0xEA
MD2 DATA 0xEB
MD3 DATA 0xEC
MD4 DATA 0xED
MD5 DATA 0xEE
UD BIT 0xD0.1
NAME SYS
ENTRY MACRO symbol
PUBLIC symbol
symbol:
ENDM
EXTRN CODE (?C?CLDPTR)
EXTRN CODE (?C?CSTPTR)
EXTRN CODE (_msWarning)
?XD??_MDrv_Sys_RunCodeInXXX?DRVSYS SEGMENT XDATA OVERLAYABLE
RSEG ?XD??_MDrv_Sys_RunCodeInXXX?DRVSYS
ENTRY ?_MDrv_Sys_CopyVAR2MIU?BYTE
ENTRY ?_MDrv_Sys_CopyMIU2VAR?BYTE
ENTRY ?_MDrv_MIU_VAR2SDRAMCopy?BYTE ; for compatible, remove later
ENTRY ?_MDrv_MIU_SDRAM2VARCopy?BYTE
ORG 7
u16Length: DS 4
?PR?_MDrv_Sys_RunCodeInXXX?DRVSYS SEGMENT CODE PAGE
RSEG ?PR?_MDrv_Sys_RunCodeInXXX?DRVSYS
USING 0
;
; Get current code bank to R0
;
GET_CODE_BANK_TO_R0:
MOV DPTR, #(REG_CODE_BANK)
MOVX A, @DPTR
MOV R0, A
RET
;
; bit MDrv_Sys_IsCodeInSPI( void );
;
ENTRY MDrv_Sys_IsCodeInSPI
;
; Return true if icache is enabled
;
MOV DPTR, #(REG_CODE_FETCH)
MOVX A, @DPTR
CLR C
SUBB A, #08EH
JC EXIT_IsCodeInSPI
CALL GET_CODE_BANK_TO_R0
;
; Get SPI Start Bank
;
MOV DPTR, #(REG_CACHE_END_1)
MOVX A, @DPTR
SUBB A, R0 ; C == 0 before SUBB
EXIT_IsCodeInSPI:
RET
;
; void MDrv_Sys_RunCodeInSPI( void );
;
; This is called in STARTUP.A51, please check the code bank setting of this file
;
ENTRY MDrv_Sys_RunCodeInSPI
CALL MDrv_Sys_IsCodeInSPI ; Now R0 is current code bank
JC DISABLE_CACHE
SWITCH_TO_SPI:
;
; Prepare for SPI
;
MOV A, R0
MOV DPTR, #(REG_CACHE_END_1)
MOVX @DPTR, A
MOV DPTR, #(REG_CACHE_END_0)
MOV A, #LOW (DISABLE_CACHE-1)
MOVX @DPTR, A
INC DPTR
MOV A, #HIGH (DISABLE_CACHE-1)
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_START_0)
MOV A, #LOW (DISABLE_CACHE)
MOVX @DPTR, A
INC DPTR
MOV A, #HIGH (DISABLE_CACHE)
MOVX @DPTR, A
MOV A, R0
MOV DPTR, #(REG_SPI_START_1)
MOVX @DPTR, A
NOP
DISABLE_CACHE:
;
; Disable and reset iCACHE
;
MOV DPTR, #(REG_CODE_FETCH)
MOV A, #082H
MOVX @DPTR, A
;
; void MDrv_Sys_ExtendSPIRange( void );
;
ENTRY MDrv_Sys_ExtendSPIRange
;
; Set SPI Start to 0x000000
;
CLR A
MOV DPTR, #(REG_SPI_START_0)
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_START_1)
MOVX @DPTR, A
SET_SPI_END_WITH_CPL_ACC:
;
; Set SPI End to 0xFFFFFF
;
MOV DPTR, #(REG_SPI_END_0)
CPL A
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_END_1)
MOVX @DPTR, A
RET
;
; void MDrv_Sys_RunCodeInMIU( U16 u16MIUAddrInBank, // R6, R7
; U8 u8NumBanks, // R5
; BOOLEAN bBypassCache ); // R3
;
FIX_CACHE_CODE_MAPPING:
;
; Set SPI Start to (u8NumBanks) :0000
; Set Cache End to (u8NumBanks-1):FFFF
;
MOV A, R5
MOV DPTR, #(REG_SPI_START_1)
MOVX @DPTR, A
DEC A
MOV DPTR, #(REG_CACHE_END_1)
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_START_0)
CLR A
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
CPL A
MOV DPTR, #(REG_CACHE_END_0)
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
RET
ENABLE_CACHE:
;
; Enable both SPI & iCACHE, also set `iCACHE no reset' bit
;
MOV DPTR, #(REG_CODE_FETCH)
MOV A, #08EH
MOVX @DPTR, A
;
; Set cache base after clear iCACHE reset
;
MOV DPTR, #(REG_CACHE_BASE)
MOV A, R7
MOVX @DPTR, A
INC DPTR
MOV A, R6
MOVX @DPTR, A
;
; Enable HKMCU iCache bypass if bBypassCache(R3) is not zero
;
MOV A, #0xFF
ADD A, R3
MOV DPTR, #(REG_CACHE_BYPASS)
MOVX A, @DPTR
MOV ACC.0, C
MOVX @DPTR, A
EXIT_RunCodeInMIU:
RET
ENTRY _MDrv_Sys_RunCodeInMIU
;
; R0: CurrCodeBank
;
;
; if (u8NumBanks == 0) do nothing
;
MOV A, R5
JZ EXIT_RunCodeInMIU
;
; Set iCache Start to 0x0
;
MOV DPTR, #(REG_CACHE_START_0)
CLR A ; 0x00
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
MOV DPTR, #(REG_CACHE_START_1)
MOVX @DPTR, A
CALL SET_SPI_END_WITH_CPL_ACC
CALL GET_CODE_BANK_TO_R0
;
; if (u8NumBanks < CurrCodeBank) transfer to cache
;
CLR C
SUBB A, R5
JC SWITCH_TO_CACHE
CALL FIX_CACHE_CODE_MAPPING
SJMP ENABLE_CACHE
SWITCH_TO_CACHE:
;
; Prepare for Cache
;
MOV DPTR, #(REG_CACHE_END_0)
MOV A, #LOW (ENABLE_CACHE-1)
MOVX @DPTR, A
INC DPTR
MOV A, #HIGH (ENABLE_CACHE-1)
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_START_0)
MOV A, #LOW (ENABLE_CACHE)
MOVX @DPTR, A
INC DPTR
MOV A, #HIGH (ENABLE_CACHE)
MOVX @DPTR, A
MOV A, R0
MOV DPTR, #(REG_CACHE_END_1)
MOVX @DPTR, A
MOV DPTR, #(REG_SPI_START_1)
MOVX @DPTR, A
CALL ENABLE_CACHE
SJMP FIX_CACHE_CODE_MAPPING
;
; U16 MDrv_Sys_SetXdataWindow1Base(U16 u16XDWin1BaseIn4Kytes); // R6 - R7
;
ENTRY _MDrv_Sys_SetXdataWindow1Base
MOV DPTR, #(REG_SDR_XD_MAP_1)
MOVX A, @DPTR
XCH A, R7
MOVX @DPTR, A
INC DPTR
MOVX A, @DPTR
XCH A, R6
MOVX @DPTR, A
RET
;
; U16 MDrv_Sys_GetXdataWindow1Base(void);
;
ENTRY MDrv_Sys_GetXdataWindow1Base
MOV DPTR, #(REG_SDR_XD_MAP_1)
MOVX A, @DPTR
MOV R7, A
INC DPTR
MOVX A, @DPTR
MOV R6, A
RET
;
; void MDrv_MIU_VAR2SDRAMCopy( U8 * pAddr, // R1 - R3
; U32 u32MiuAddr, // R4 - R7
; U32 u32Length )
;
ENTRY _MDrv_MIU_VAR2SDRAMCopy
MOV DPTR, #(u16Length + 2)
MOVX A, @DPTR
MOV DPTR, #(u16Length)
MOVX @DPTR, A
MOV DPTR, #(u16Length + 3)
MOVX A, @DPTR
MOV DPTR, #(u16Length + 1)
MOVX @DPTR, A
SJMP _MDrv_Sys_CopyVAR2MIU
;
; void MDrv_MIU_SDRAM2VARCopy( U32 u32MiuAddr, // R4 - R7
; U8 * pAddr, // R1 - R3
; U32 u32Length )
;
ENTRY _MDrv_MIU_SDRAM2VARCopy
MOV DPTR, #(u16Length + 2)
MOVX A, @DPTR
MOV DPTR, #(u16Length)
MOVX @DPTR, A
MOV DPTR, #(u16Length + 3)
MOVX A, @DPTR
MOV DPTR, #(u16Length + 1)
MOVX @DPTR, A
SJMP _MDrv_Sys_CopyMIU2VAR
;
; void MDrv_Sys_CopyVAR2MIU( U8 * pAddr, // R1 - R3
; U32 u32MiuAddr, // R4 - R7
; U16 u16Length )
;
ENTRY _MDrv_Sys_CopyVAR2MIU
CLR UD
SJMP _MDrv_Sys_Copy
;
; void MDrv_Sys_CopyMIU2VAR( U32 u32MiuAddr, // R4 - R7
; U8 * pAddr, // R1 - R3
; U16 u16Length )
;
ENTRY _MDrv_Sys_CopyMIU2VAR
SETB UD
SJMP _MDrv_Sys_Copy
;
; void MDrv_Sys_Copy( U8 * pAddr, // R1 - R3
; U32 u32MiuAddr, // R4 - R7
; U16 u16Length )
;
_MDrv_Sys_Copy:
;
; R1/R2/R3: pAddr
; R4/R5: block length
; R6/R7: total length
;
;
; u32MiuAddr / 0x1000
;
MOV MD0, R7 ; D'endL
MOV MD1, R6
MOV MD2, R5
MOV MD3, R4 ; D'endH
MOV MD4, #LOW (0x1000) ; D'orL
MOV MD5, #HIGH (0x1000) ; D'orH
;
; Store u16Length to R6/R7
;
MOV DPTR, #u16Length
MOVX A, @DPTR
MOV R6, A
INC DPTR
MOVX A, @DPTR
MOV R7, A
;
; Backup xdata win1 base, and set new one
;
MOV DPTR, #(REG_SDR_XD_MAP_1)
MOVX A, @DPTR
PUSH ACC
MOV A, MD0
MOVX @DPTR, A
INC DPTR
MOVX A, @DPTR
PUSH ACC
MOV A, MD1
MOVX @DPTR, A
;
; DPTR = (Remainder + 0xF000)
; R4/R5 = (0x1000 - Reminder)
;
MOV A, MD4 ; RemL
MOV DPL, A
CPL A
ADD A, #01H
MOV R5, A
MOV A, MD5 ; RemH
ORL A, #0xF0
MOV DPH, A
CPL A
ADDC A, #00H
MOV R4, A
COPY_BLOCK:
MOV A, R7
CJNE R6, #00H, COMPARE_LENGTH_AND_BLOCK
JZ COPY_EXIT
COMPARE_LENGTH_AND_BLOCK: ; C == 0 now, see above CJNE
SUBB A, R5
MOV A, R6
SUBB A, R4
JNC LENGTH_MINUS_BLOCK
ASSIGN_LEHGTH_TO_BLOCK:
MOV R4, AR6
MOV R5, AR7
LENGTH_MINUS_BLOCK:
CLR C
MOV A, R7
SUBB A, R5
MOV R7, A
MOV A, R6
SUBB A, R4
MOV R6, A
MOV A, R5
JZ COPY_BYTE
INC R4
COPY_BYTE:
JB UD, COPY_BYTE_MIU2VAR
COPY_BYTE_VAR2MIU:
XRL DPS, #01H
LCALL ?C?CLDPTR
XRL DPS, #01H
MOVX @DPTR, A
INC DPTR
INC R1
CJNE R1, #00, PTR_NOT_CARRY_0
INC R2
PTR_NOT_CARRY_0:
DJNZ R5, COPY_BYTE_VAR2MIU
DJNZ R4, COPY_BYTE_VAR2MIU
SJMP END_OF_COPY_BLOCK
COPY_BYTE_MIU2VAR:
MOVX A, @DPTR
INC DPTR
XRL DPS, #01H
LCALL ?C?CSTPTR
XRL DPS, #01H
INC R1
CJNE R1, #00, PTR_NOT_CARRY_1
INC R2
PTR_NOT_CARRY_1:
DJNZ R5, COPY_BYTE_MIU2VAR
DJNZ R4, COPY_BYTE_MIU2VAR
END_OF_COPY_BLOCK:
MOV A, DPH
JNZ COPY_EXIT
;
; update window1 base
;
MOV DPTR, #(REG_SDR_XD_MAP_1)
MOVX A, @DPTR
INC A
MOVX @DPTR, A
JNZ BASE_NOT_CARRY
INC DPTR
MOVX A, @DPTR
INC A
MOVX @DPTR, A
BASE_NOT_CARRY:
MOV DPTR, #0xF000
MOV R4, #010H
SJMP COPY_BLOCK
COPY_EXIT:
;
; Restore xdata win1 base
;
MOV DPTR, #(REG_SDR_XD_MAP_1 + 1)
POP ACC
MOVX @DPTR, A
MOV DPTR, #(REG_SDR_XD_MAP_1)
POP ACC
MOVX @DPTR, A
RET
END⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -