📄 drvadc.c

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    }
}

void MDrv_ADC_Init(void)
{
    MDrv_WriteRegTbl( ADC_Init_Tbl );
    XBYTE[PLL_CONTROL_IN_ATOP]=(XBYTE[PLL_CONTROL_IN_ATOP] & 0x80)|0x06;
}

void MDrv_ADC_SetSogFilter(U8 u8PixClk)
{
    /* set SOG filter */
    if (u8PixClk > ADC_SOG_FILTER_THRSHLD)
    {
        MDrv_WriteRegBit(BK_ADC_ATOP_1C_H, FALSE, _BIT3);
    }
    else
    {
        MDrv_WriteRegBit(BK_ADC_ATOP_1C_H, TRUE, _BIT3);
    }
}

void MDrv_ADC_SetClampDuration(U8 u8Value)
{
    /* reg_clamp_dur */
    MDrv_WriteByte(BK_ADC_DTOP_0B_H, u8Value);
}

void MDrv_ADC_SetClampPlacement(U8 u8Value)
{
    /* reg_clamp_dly */
    MDrv_WriteByte(BK_ADC_DTOP_0B_L, u8Value);
}

void MDrv_ADC_SetInputHsyncPolarity(BOOLEAN bHightActive,EN_INPUT_PORT_TYPE enInputPortType)
{
	switch(enInputPortType)
	{
		case INPUT_PORT_ADC_A_RGB:
		case INPUT_PORT_ADC_A_YPBPR:
            MDrv_WriteRegBit(BK_ADC_DTOP_07_L, bHightActive, _BIT7);
		break;

		case INPUT_PORT_ADC_B_RGB:
		case INPUT_PORT_ADC_B_YPBPR:
			MDrv_WriteRegBit(BK_ADC_DTOP_27_L, bHightActive, _BIT7);
		break;
	}
}

void MDrv_ADC_SetForDvi(void)
{
    MDrv_Write2Byte(BK_ADC_ATOP_1C_L, 0x0000); // ADC bandwidth
    MDrv_WriteByte(BK_ADC_DTOP_01_L, 0x81); // PLL loop filter control
}

//-----------------------------------------------------------------------------
// ADC power
//-----------------------------------------------------------------------------

void MDrv_ADC_PowerOn(MS_ADC_POWER_ON_TYPE enADCPowerType)
{
    U8 u8ADC_Power_04L = ADC_POWERINIT_MSK_04_L;
    U8 u8ADC_Power_04H = ADC_POWERINIT_MSK_04_H;
    U8 u8ADC_Power_05L = ADC_POWERINIT_MSK_05_L;
    U8 u8ADC_Power_05H=0x00;
    U8 u8ADC_Power_06L = ADC_POWERINIT_MSK_06_L;
    U8 u8ADC_Power_06H = ADC_POWERINIT_MSK_06_H;
    U8 u8ADC_Power_60L = ADC_POWERINIT_MSK_60_L;
    U8 u8ADC_Power_60H = ADC_POWERINIT_MSK_60_H;
    U8 u8ADC_Power_40L_6 = 1;

    switch (enADCPowerType)
    {

// seven 070828_00
    case MS_ADC_A_POWER_ON:
        u8ADC_Power_04L |= (_BIT5|_BIT4|_BIT3|_BIT2|_BIT1|_BIT0);
        u8ADC_Power_04H |= 0x00;
        u8ADC_Power_05L |= _BIT5;
        u8ADC_Power_05H |= _BIT1;
        u8ADC_Power_06L |= (_BIT3|_BIT2|_BIT1);
        break;

	case MS_ADC_B_POWER_ON:
        u8ADC_Power_04L = 0xC0;
        u8ADC_Power_04H = 0x3F;
        u8ADC_Power_06L = 0x32;
        u8ADC_Power_06H = 0x00;
        break;
// end

    case MS_VDA_CVBS_POWER_ON: // seven
        u8ADC_Power_04H |= (_BIT7|_BIT4|_BIT2|_BIT1|_BIT0);
        u8ADC_Power_05L |= (_BIT4|_BIT3|_BIT2|_BIT1);
        u8ADC_Power_06L |= (_BIT7|_BIT6|_BIT5);
        break;

    case MS_VDA_SV_POWER_ON: // seven
        u8ADC_Power_04H |= (_BIT7|_BIT6|_BIT4|_BIT3|_BIT2|_BIT1|_BIT0);
        u8ADC_Power_05L |= (_BIT4|_BIT3|_BIT2|_BIT1|_BIT0);
        u8ADC_Power_06L |= (_BIT7|_BIT6|_BIT5);
        break;

    case MS_VDA_FBLANK_POWER_ON:
        u8ADC_Power_04L |= (_BIT5|_BIT4|_BIT3|_BIT2|_BIT1);
        u8ADC_Power_04H |= (_BIT7|_BIT4|_BIT1);
        u8ADC_Power_05L |= (_BIT4|_BIT3|_BIT1);
        u8ADC_Power_06L |= (_BIT7|_BIT6|_BIT3|_BIT2|_BIT1);
        u8ADC_Power_06H |= (_BIT6);
        u8ADC_Power_40L_6 = 0;
        break;

    case MS_DVI_POWER_ON:
        u8ADC_Power_06H |= (_BIT7|_BIT5|_BIT3|_BIT1|_BIT0);
        u8ADC_Power_60L |= (_BIT7|_BIT5|_BIT3|_BIT2|_BIT1|_BIT0);
        u8ADC_Power_60H |= (_BIT5|_BIT3|_BIT2|_BIT1|_BIT0);
        break;

    case MS_ADC_VD_BLEND_POWER_ON:
        u8ADC_Power_04L |= (_BIT5|_BIT4|_BIT3|_BIT2|_BIT1);
        u8ADC_Power_04H |= (_BIT7|_BIT4|_BIT1);
        u8ADC_Power_05L |= (_BIT4|_BIT3|_BIT1);
        u8ADC_Power_06L |= (_BIT7|_BIT6|_BIT3|_BIT2|_BIT1);
        u8ADC_Power_06H |= (_BIT6);
        u8ADC_Power_40L_6 = 0;
        break;

     default:
        break;
    }

    MDrv_WriteByte(BK_ADC_ATOP_04_L, (0xFF & ~(u8ADC_Power_04L)));
    MDrv_WriteByte(BK_ADC_ATOP_04_H, (0xFF & ~(u8ADC_Power_04H)));
    MDrv_WriteByte(BK_ADC_ATOP_05_L, (0xFF & ~(u8ADC_Power_05L)));
    MDrv_WriteByte(BK_ADC_ATOP_06_L, (0xFF & ~(u8ADC_Power_06L)));
    MDrv_WriteByte(BK_ADC_ATOP_06_H, (0xFF & ~(u8ADC_Power_06H)));
    MDrv_WriteByte(BK_ADC_ATOP_60_L, (0xFF & ~(u8ADC_Power_60L)));
    MDrv_WriteByte(BK_ADC_ATOP_60_H, (0xFF & ~(u8ADC_Power_60H)));
    MDrv_WriteByteMask(BK_ADC_ATOP_40_L, u8ADC_Power_40L_6, _BIT6);
}

void MDrv_ADC_PowerOff(void)
{
    MDrv_WriteByte(BK_ADC_ATOP_04_L, 0xFE);         // Bit-0 is relative to DRAM.
    MDrv_WriteByte(BK_ADC_ATOP_04_H, 0xFF);
    MDrv_WriteByte(BK_ADC_ATOP_05_L, 0xFF);
    MDrv_WriteByte(BK_ADC_ATOP_06_L, 0xFF);
    MDrv_WriteByte(BK_ADC_ATOP_06_H, 0xFF);
    MDrv_WriteByte(BK_ADC_ATOP_60_L, 0xEF);         // Bit-4 is relative to DRAM
    MDrv_WriteByte(BK_ADC_ATOP_60_H, 0xFF);
    MDrv_WriteByte(BK_ADC_ATOP_70_L, 0x0F);         // reg_cvbso1_pd
//    MDrv_WriteByteMask(BK_ADC_ATOP_08_L, 1, _BIT4);   // Cannot turn off MPLL
    MDrv_WriteByteMask(BK_ADC_ATOP_4C_L, 1, _BIT5);
    MDrv_WriteByteMask(BK_ADC_ATOP_40_L, 1, _BIT6);
}

//-----------------------------------------------------------------------------
// MUX
//-----------------------------------------------------------------------------

MS_ADC_POWER_ON_TYPE MDrv_ADC_SetMUX(EN_INPUT_PORT_TYPE enInputPortType, U8 u8InputSrcMux, U8 u8VDYMux, U8 u8VDCMux)
{
    MS_ADC_POWER_ON_TYPE enADCPowerType = MS_ADC_POWER_ALL_OFF;

    U8 u8Src_En = 0;

	u8InputSrcMux = u8InputSrcMux;

    ADCMSG(printf("\r\nSet ADC Mux"));
    ADCMSG(printf("\r\nenInputPortType=0x%bx", enInputPortType));

	// seven 070828_00
    if(IsUseAnalogPort(enInputPortType))
    {
		switch(enInputPortType)
		{
			case INPUT_PORT_ADC_A_RGB:
			case INPUT_PORT_ADC_A_YPBPR:
                u8Src_En |= En_ADC_A;
                enADCPowerType = MS_ADC_A_POWER_ON;
                break;

			case INPUT_PORT_ADC_B_RGB:
			case INPUT_PORT_ADC_B_YPBPR:
			u8Src_En |= En_ADC_B;
			enADCPowerType = MS_ADC_B_POWER_ON;
			break;
		}
    }
	// end

#if (ENABLE_SCART_VIDEO)
    else if(IsUseInternalScartPort(enInputPortType))
    {
        u8Src_En |= En_VD|En_FB_RGB;
        enADCPowerType = MS_VDA_FBLANK_POWER_ON;
    }
#endif
    else if(IsUseInternalSVPort(enInputPortType))
    {
        u8Src_En |= En_VD;//|En_VD_YC|En_FB_RGB; // seven
        enADCPowerType = MS_VDA_SV_POWER_ON;
    }
    else if(IsUseInternalAVPort(enInputPortType)) // seven
    {
        u8Src_En |= En_VD;
        //u8Src_En &= ~En_ADC_AMUX; seven
        enADCPowerType = MS_VDA_CVBS_POWER_ON;
    }
    else
    {
        u8Src_En |= En_VD;
        //u8Src_En &= ~En_ADC_AMUX; seven
        enADCPowerType = MS_VDA_CVBS_POWER_ON;
    }

    u8VDCMux &= 0x0F;
    u8VDYMux &= 0x0F;

    ADCMSG(printf("\r\nu8Src_En=0x%bx", u8Src_En));
    ADCMSG(printf("\r\nu8VDCMux=0x%bx", u8VDCMux));
    ADCMSG(printf("\r\nu8VDYMux=0x%bx", u8VDYMux));

    if(IsUseAnalogPort(enInputPortType)) // seven
    {
    	// seven 070823_00
		switch(enInputPortType)
		{
			case INPUT_PORT_ADC_A_RGB:
		        MDrv_WriteRegBit(BK_ADC_ATOP_01_L,FALSE,BIT0);

				/* Vclamp */
				MDrv_WriteByte(BK_ADC_ATOP_2C_L,0x04); // G clamp to VP3

				MDrv_WriteRegBit(BK_ADC_DTOP_07_L,FALSE,BIT6);

				/* PLL phase setting time */
//				MDrv_WriteByteMask(BK_ADC_DTOP_04_L, 0x05, _BIT3 | _BIT2 | _BIT1 | _BIT0 );
				/* clamp placement */
//				MDrv_WriteByte(BK_ADC_DTOP_0B_L, 0x10);
				/* clamp duration */
//				MDrv_WriteByte(BK_ADC_DTOP_0B_H, 0x08);
			break;

			case INPUT_PORT_ADC_A_YPBPR:
		        MDrv_WriteRegBit(BK_ADC_ATOP_01_L,TRUE,BIT0);

				/* Vclamp */
				MDrv_WriteByte(BK_ADC_ATOP_2C_L,0x26);

				MDrv_WriteRegBit(BK_ADC_DTOP_07_L,TRUE,BIT6);

				/* PLL phase setting time */
//				MDrv_WriteByteMask(BK_ADC_DTOP_04_L, 0x08, _BIT3 | _BIT2 | _BIT1 | _BIT0 );
				/* clamp placement */
//				MDrv_WriteByte(BK_ADC_DTOP_0B_L, 0x30);
				/* clamp duration */
//				MDrv_WriteByte(BK_ADC_DTOP_0B_H, 0x05);
			break;

			case INPUT_PORT_ADC_B_RGB:
		        MDrv_WriteRegBit(BK_ADC_ATOP_01_L,FALSE,BIT2);
				/* Vclamp */
				MDrv_WriteByte(BK_ADC_ATOP_2C_H,0x04); // G clamp to VP3

				MDrv_WriteRegBit(BK_ADC_DTOP_27_L,FALSE,BIT6);

				/* PLL phase setting time */
//				MDrv_WriteByteMask(BK_ADC_DTOP_24_L, 0x05, _BIT3 | _BIT2 | _BIT1 | _BIT0 );
				/* clamp placement */
//				MDrv_WriteByte(BK_ADC_DTOP_2B_L, 0x10);
				/* clamp duration */
//				MDrv_WriteByte(BK_ADC_DTOP_2B_H, 0x08);
			break;

			case INPUT_PORT_ADC_B_YPBPR:
		        MDrv_WriteRegBit(BK_ADC_ATOP_01_L,TRUE,BIT2);

				/* Vclamp */
				MDrv_WriteByte(BK_ADC_ATOP_2C_H,0x26);

				MDrv_WriteRegBit(BK_ADC_DTOP_27_L,TRUE,BIT6);

				/* PLL phase setting time */
//				MDrv_WriteByteMask(BK_ADC_DTOP_24_L, 0x08, _BIT3 | _BIT2 | _BIT1 | _BIT0 );
				/* clamp placement */
//				MDrv_WriteByte(BK_ADC_DTOP_2B_L, 0x30);
				/* clamp duration */
//				MDrv_WriteByte(BK_ADC_DTOP_2B_H, 0x05);
			break;
		}
		// end
    }
#if (ENABLE_SCART_VIDEO)
    else if(IsUseInternalScartPort(enInputPortType))
    {
        MDrv_WriteByteMask(BK_ADC_ATOP_01_L, u8VDCMux,_BIT0|_BIT1); // select RGB channel
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, u8VDYMux, ADC_YMUX_MASK); // ADC_VD_YMUX_MASK  for CVBS
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, (u8VDCMux<<4), ADC_CMUX_MASK); // ADC_VD_CMUX_MASK
    }
#endif
    else if(IsUseInternalSVPort(enInputPortType))
    {
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, u8VDYMux, ADC_YMUX_MASK);
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, (u8VDCMux << 4), ADC_CMUX_MASK);
    }
    else if(IsUseInternalAVPort(enInputPortType)) // seven
    {
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, u8VDYMux, ADC_YMUX_MASK);
        MDrv_WriteByteMask(BK_ADC_ATOP_02_L, (u8VDCMux << 4), ADC_CMUX_MASK);
    }

    MDrv_WriteByte(BK_ADC_ATOP_00_L, u8Src_En);

    ADCMSG(printf("\r\nenADCPowerType=0x%bx", enADCPowerType));

    return enADCPowerType;
}

//-----------------------------------------------------------------------------
// config
//-----------------------------------------------------------------------------

#undef DRV_ADC_C
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